diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 5dd5b64..3fcb5b5 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -405,7 +405,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   ))
 
   datar := MuxCase( 0.U, Array(
-      ((addrr & "hF800".U) === "h0000".U) -> AcquireReg(addr = addrr),
+      ((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), isEnR ),
       ((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar,
       ((addrr & "hF800".U) === "h1000".U) -> 0.U,
       ((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar,
diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index d7d9b61..8a9c339 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -71,7 +71,7 @@ abstract class SpiInterfaceBase extends Module{
   io.addrw := addrw
   // io.addrSel :=
   //   Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
-  val readData = RegEnable(io.datar, io.isEnR)
+  // val readData = RegEnable(io.datar, io.isEnR)
   
 
   when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -152,7 +152,7 @@ class SSpiInterface extends SpiInterfaceBase{
       when((byteSel === 1.U || byteSel === 2.U) ){
         exRego := 0.U //地址1，cmd
       } .elsewhen( isSpiRead ){
-        exRego := readData
+        exRego := io.datar
       }
     }.otherwise{
       exRego := exRego << 1
@@ -195,7 +195,7 @@ class QSpiInterface extends SpiInterfaceBase{
       when((byteSel === 1.U || byteSel === 2.U) ){
         exRego := 0.U //地址1，cmd
       } .elsewhen( isSpiRead ){
-        exRego := readData
+        exRego := io.datar
       }
     }.otherwise{
       exRego := exRego << 4