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恢复使用定时器复位

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This commit is contained in:
RuigeLee
2024-05-22 10:20:48 +08:00
parent cf76ef1595
commit 59e708a2af
2 changed files with 20 additions and 8 deletions
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13
src/main/verilog/di16_top.v
View File

@@ -1,9 +1,7 @@
module di16_top(
input clock,
input resetn,
input lvds_up_din_p,
input lvds_up_din_n,
@@ -15,6 +13,7 @@ module di16_top(
output lvds_down_dout_p,
output lvds_down_dout_n,
input DCIn,
output isOnline,
input isLast,
@@ -23,8 +22,6 @@ module di16_top(
);
wire DCIn = 1'b0;
wire clk_400m;
wire clk_400m_a;
wire clk_100m_a;
@@ -38,8 +35,16 @@ wire reset_calib;
reg rst_n;
reg rstn_d;
wire resetn;
reg [3:0] resetCnt = 4'd0;
always @( posedge clock ) begin
if( resetCnt != 4'd15 ) begin
resetCnt <= resetCnt + 4'd1;
end
end
assign resetn = resetCnt == 4'd15;
always@(posedge clk_10m_a) begin
rstn_d <= resetn;

15
src/main/verilog/do16_top.v
View File

@@ -3,7 +3,7 @@
module do16_top(
input clock,
input resetn,
input lvds_up_din_p,
input lvds_up_din_n,
@@ -18,7 +18,7 @@ module do16_top(
output isOnline,
input isLast,
input DCIn,
output LED_PR,
output [15:0] out,
input flt_0,
@@ -26,7 +26,7 @@ module do16_top(
);
wire DCIn = 1'b0;
wire clk_400m;
wire clk_400m_a;
@@ -41,9 +41,16 @@ wire reset_calib;
reg rst_n;
reg rstn_d;
wire resetn;
reg [3:0] resetCnt = 4'd0;
always @( posedge clock ) begin
if( resetCnt != 4'd15 ) begin
resetCnt <= resetCnt + 4'd1;
end
end
assign resetn = resetCnt == 4'd15;
always@(posedge clk_10m_a) begin
rstn_d <= resetn;