diff --git a/src/main/verilog/di16_top.v b/src/main/verilog/di16_top.v
index c74d5ee..fea6d09 100644
--- a/src/main/verilog/di16_top.v
+++ b/src/main/verilog/di16_top.v
@@ -1,9 +1,7 @@
 
 
 module di16_top(
-
   input clock,
-  input resetn,
      
   input  lvds_up_din_p,
   input  lvds_up_din_n, 
@@ -15,6 +13,7 @@ module di16_top(
   output lvds_down_dout_p,
   output lvds_down_dout_n,
 
+  input DCIn,
   output isOnline,
   input  isLast,
 
@@ -23,8 +22,6 @@ module di16_top(
 
 );
 
-wire  DCIn = 1'b0;
-
 wire clk_400m;
 wire clk_400m_a;
 wire clk_100m_a;
@@ -38,8 +35,16 @@ wire reset_calib;
 reg rst_n;
 reg rstn_d;
 
+wire resetn;
 
+reg [3:0] resetCnt = 4'd0;
+always @( posedge clock ) begin
+  if( resetCnt != 4'd15 ) begin
+    resetCnt <= resetCnt + 4'd1;
+  end
+end
 
+assign resetn = resetCnt == 4'd15;
 
 always@(posedge clk_10m_a) begin
   rstn_d <= resetn;
diff --git a/src/main/verilog/do16_top.v b/src/main/verilog/do16_top.v
index 5a2beee..fd6e200 100644
--- a/src/main/verilog/do16_top.v
+++ b/src/main/verilog/do16_top.v
@@ -3,7 +3,7 @@
 module do16_top(
 
   input clock,
-  input resetn,
+
      
   input  lvds_up_din_p,
   input  lvds_up_din_n, 
@@ -18,7 +18,7 @@ module do16_top(
   output isOnline,
   input  isLast,
 
-
+  input DCIn,
   output        LED_PR,
   output [15:0] out,
   input         flt_0,
@@ -26,7 +26,7 @@ module do16_top(
 
 );
 
-wire  DCIn = 1'b0;
+
 
 wire clk_400m;
 wire clk_400m_a;
@@ -41,9 +41,16 @@ wire reset_calib;
 reg rst_n;
 reg rstn_d;
 
+wire resetn;
 
+reg [3:0] resetCnt = 4'd0;
+always @( posedge clock ) begin
+  if( resetCnt != 4'd15 ) begin
+    resetCnt <= resetCnt + 4'd1;
+  end
+end
 
-
+assign resetn = resetCnt == 4'd15;
 
 always@(posedge clk_10m_a) begin
   rstn_d <= resetn;