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直接用IO信号判断，不用跳变沿，写更新需要改

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RuigeLee
2024-03-21 10:51:37 +08:00
parent e53687e11d
commit 59103b6848
1 changed files with 7 additions and 7 deletions
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14
src/main/scala/backBoard/BackBoardMst.scala
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@@ -101,14 +101,14 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
withClockAndReset( io.ides_pclk.asClock, reset ){//100M withClockAndReset( io.ides_pclk.asClock, reset ){//100M
val fsmcCSSync = ShiftRegisters( ~io.FSMC.csn, 3, false.B, true.B ) // val fsmcCSSync = ShiftRegisters( ~io.FSMC.csn, 3, false.B, true.B )
val fsmcRDSync = ShiftRegisters( ~io.FSMC.rdn, 3, false.B, true.B ) // val fsmcRDSync = ShiftRegisters( ~io.FSMC.rdn, 3, false.B, true.B )
val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B ) // val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B )
val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B ) // val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )
io.FSMC.ADOEn := fsmcRDSync(0) & fsmcCSSync(0) & ~fsmcADVSync(0) io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn //fsmcRDSync(0) & fsmcCSSync(0) & ~fsmcADVSync(0)
val latchAddr = RegEnable( io.FSMC.ADIn, (~fsmcADVSync(1) & fsmcADVSync(0) & fsmcCSSync(0)) | (fsmcADVSync(0) & ~fsmcCSSync(1) & fsmcCSSync(0)) ) val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)//(~fsmcADVSync(1) & fsmcADVSync(0) & fsmcCSSync(0)) | (fsmcADVSync(0) & ~fsmcCSSync(1) & fsmcCSSync(0)) )
val isAccessSRAM = ~latchAddr.extract(10) val isAccessSRAM = ~latchAddr.extract(10)
val isAccessReg = latchAddr.extract(10) val isAccessReg = latchAddr.extract(10)
@@ -154,7 +154,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
when( isAccessReg & fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){ when( isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn ){ //fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
isRegRefleshFlip := ~isRegRefleshFlip isRegRefleshFlip := ~isRegRefleshFlip
wrRegAddr := activeAddr wrRegAddr := activeAddr
wrRegData := io.FSMC.ADIn wrRegData := io.FSMC.ADIn