diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index d79da79..380e375 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -101,14 +101,14 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
   withClockAndReset( io.ides_pclk.asClock, reset ){//100M
 
 
-    val fsmcCSSync  = ShiftRegisters( ~io.FSMC.csn,  3, false.B, true.B )
-    val fsmcRDSync  = ShiftRegisters( ~io.FSMC.rdn,  3, false.B, true.B )
-    val fsmcWRSync  = ShiftRegisters( ~io.FSMC.wrn,  3, false.B, true.B )
-    val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )  
+    // val fsmcCSSync  = ShiftRegisters( ~io.FSMC.csn,  3, false.B, true.B )
+    // val fsmcRDSync  = ShiftRegisters( ~io.FSMC.rdn,  3, false.B, true.B )
+    // val fsmcWRSync  = ShiftRegisters( ~io.FSMC.wrn,  3, false.B, true.B )
+    // val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )  
 
-    io.FSMC.ADOEn := fsmcRDSync(0) & fsmcCSSync(0) & ~fsmcADVSync(0)
+    io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn //fsmcRDSync(0) & fsmcCSSync(0) & ~fsmcADVSync(0)
 
-    val latchAddr = RegEnable( io.FSMC.ADIn, (~fsmcADVSync(1) & fsmcADVSync(0) & fsmcCSSync(0)) | (fsmcADVSync(0) & ~fsmcCSSync(1) & fsmcCSSync(0)) )
+    val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)//(~fsmcADVSync(1) & fsmcADVSync(0) & fsmcCSSync(0)) | (fsmcADVSync(0) & ~fsmcCSSync(1) & fsmcCSSync(0)) )
 
     val isAccessSRAM = ~latchAddr.extract(10) 
     val isAccessReg  =  latchAddr.extract(10)
@@ -154,7 +154,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
 
 
-    when( isAccessReg & fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
+    when( isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn ){ //fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
       isRegRefleshFlip := ~isRegRefleshFlip
       wrRegAddr        := activeAddr
       wrRegData        := io.FSMC.ADIn