From 59103b6848cc70c88e777adb4224dc7ac097626a Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 21 Mar 2024 10:51:37 +0800 Subject: [PATCH] =?UTF-8?q?=E7=9B=B4=E6=8E=A5=E7=94=A8IO=E4=BF=A1=E5=8F=B7?= =?UTF-8?q?=E5=88=A4=E6=96=AD=EF=BC=8C=E4=B8=8D=E7=94=A8=E8=B7=B3=E5=8F=98?= =?UTF-8?q?=E6=B2=BF=EF=BC=8C=E5=86=99=E6=9B=B4=E6=96=B0=E9=9C=80=E8=A6=81?= =?UTF-8?q?=E6=94=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/BackBoardMst.scala | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala index d79da79..380e375 100644 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ b/src/main/scala/backBoard/BackBoardMst.scala @@ -101,14 +101,14 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase => withClockAndReset( io.ides_pclk.asClock, reset ){//100M - val fsmcCSSync = ShiftRegisters( ~io.FSMC.csn, 3, false.B, true.B ) - val fsmcRDSync = ShiftRegisters( ~io.FSMC.rdn, 3, false.B, true.B ) - val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B ) - val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B ) + // val fsmcCSSync = ShiftRegisters( ~io.FSMC.csn, 3, false.B, true.B ) + // val fsmcRDSync = ShiftRegisters( ~io.FSMC.rdn, 3, false.B, true.B ) + // val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B ) + // val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B ) - io.FSMC.ADOEn := fsmcRDSync(0) & fsmcCSSync(0) & ~fsmcADVSync(0) + io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn //fsmcRDSync(0) & fsmcCSSync(0) & ~fsmcADVSync(0) - val latchAddr = RegEnable( io.FSMC.ADIn, (~fsmcADVSync(1) & fsmcADVSync(0) & fsmcCSSync(0)) | (fsmcADVSync(0) & ~fsmcCSSync(1) & fsmcCSSync(0)) ) + val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)//(~fsmcADVSync(1) & fsmcADVSync(0) & fsmcCSSync(0)) | (fsmcADVSync(0) & ~fsmcCSSync(1) & fsmcCSSync(0)) ) val isAccessSRAM = ~latchAddr.extract(10) val isAccessReg = latchAddr.extract(10) @@ -154,7 +154,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase => - when( isAccessReg & fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){ + when( isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn ){ //fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){ isRegRefleshFlip := ~isRegRefleshFlip wrRegAddr := activeAddr wrRegData := io.FSMC.ADIn