txfinish转换为txfinish，同频模式有效
加入发送接收中断 cdr模块例化代码规范化
This commit is contained in:
Ruige Lee
@@ -6,35 +6,63 @@ import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
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abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
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case object BackParamsKey extends Field[BackSetting]
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// abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
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// abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
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case class BackSetting(
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){
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// case object BackParamsKey extends Field[BackSetting]
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}
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// case class BackSetting(
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// ){
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trait HasBackParameters {
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implicit val p: Parameters
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// }
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val backSetting = p(BackParamsKey)
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// trait HasBackParameters {
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// implicit val p: Parameters
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// val backSetting = p(BackParamsKey)
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// }
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// class BackCfg extends Config((_, _, _) => {
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// case BackParamsKey => BackSetting()
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// })
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class TL2CDR(implicit p: Parameters) extends LazyModule{
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val device = new SimpleDevice("TL_CDR", Nil)
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val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
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managers = Seq(
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TLSlaveParameters.v2(
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address = Seq(AddressSet(0x10000000L, 0xffffL)), //64K
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name = Some("TL_CDR"),
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regionType = RegionType.VOLATILE,
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resources = device.reg,
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executable = false,
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fifoId = Some(0),
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supports = TLMasterToSlaveTransferSizes(
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get = TransferSizes(1, 32/8),
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putFull = TransferSizes(1, 32/8),
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putPartial = TransferSizes(1, 32/8),
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),
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)
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),
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beatBytes = 32/8)))
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val int_node = IntSourceNode(IntSourcePortSimple(num = 12, resources = device.int))
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lazy val module: TL2CDRImpl = new TL2CDRImpl(this)
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}
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class BackCfg extends Config((_, _, _) => {
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case BackParamsKey => BackSetting()
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})
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abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
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abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends LazyModuleImp(outer) {
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class TLCDRIO extends Bundle{
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val overCLK = Input(Bool())
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val dDatIn = Input(Bool())
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@@ -42,17 +70,15 @@ abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Ba
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val uDatIn = Input(Bool())
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val uDatOut = Output(Bool())
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val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
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val tld = new DecoupledIO(new TLBundleD(edge.bundle))
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val interrupt = Output(Vec(8, Bool()))
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val isOnline = Output(Bool())
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val isLast = Input(Bool())
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}
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val io: TLCDRIO = IO(new TLCDRIO)
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val ( int, _ ) = outer.int_node.out(0)
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val ( bus, edge ) = outer.node.in.head
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val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
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CDRIn(0).io.serDat := io.dDatIn
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@@ -69,17 +95,17 @@ abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Ba
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val txFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) }
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val rxFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) }
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val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) } //io.tla.fire & io.tla.bits.address(5,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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val isTLReadStatus = Wire( Bool() ) //io.tla.fire & io.tla.bits.address(5,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
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val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) }
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val isTLReadStatus = Wire( Bool() )
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}
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trait TL2CDRTx{ this: TL2CDRBase =>
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trait TL2CDRImplTx{ this: TL2CDRImplBase =>
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val isTLWriteTxLen = for( i <- 0 until 2 ) yield { Wire( Bool()) }//io.tla.fire & io.tla.bits.address(5,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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val isTLWriteTxFifo = for( i <- 0 until 2 ) yield { Wire( Bool()) }//io.tla.fire & io.tla.bits.address(5,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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val isTLWriteTxLen = for( i <- 0 until 2 ) yield { Wire( Bool()) }
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val isTLWriteTxFifo = for( i <- 0 until 2 ) yield { Wire( Bool()) }
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val isTxFifoRelease = for( i <- 0 until 2 ) yield { Wire( Bool()) }
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@@ -88,9 +114,9 @@ trait TL2CDRTx{ this: TL2CDRBase =>
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val isTxFull = for( i <- 0 until 2 ) yield { ~txFifo(i).io.enq.ready }
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val intTxFifoFull = for( i <- 0 until 2 ) yield { ~RegNext(isTxFull(i), false.B) & isTxFull(i) }
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val intTxFinish = for( i <- 0 until 2 ) yield { CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast }
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val intTxEnd = for( i <- 0 until 2 ) yield { ShiftRegister( intTxFinish(i), 6, false.B, true.B) }
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// val intTxEnd = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B)
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val intTxFifoDeq = for( i <- 0 until 2 ) yield { txFifo(i).io.deq.fire }
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// println("Warning, TxEnd no confident\n")
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@@ -136,12 +162,12 @@ trait TL2CDRTx{ this: TL2CDRBase =>
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when( isTLWriteTxLen(i) ){
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txLen(i) := io.tla.bits.data
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txLen(i) := bus.a.bits.data
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} .elsewhen( CDROut(i).io.axis.fire ){
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txLen(i) := txLen(i) - 1.U
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}
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txFifo(i).io.enq.bits := io.tla.bits.data
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txFifo(i).io.enq.bits := bus.a.bits.data
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txFifo(i).io.enq.valid := isTLWriteTxFifo(i) & txLen(i) =/= 0.U
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}
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@@ -150,21 +176,22 @@ trait TL2CDRTx{ this: TL2CDRBase =>
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}
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trait TL2CDRRx{ this: TL2CDRBase =>
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trait TL2CDRImplRx{ this: TL2CDRImplBase =>
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val isTLReadRxLen = for( i <- 0 until 2 ) yield { Wire(Bool()) }//io.tla.fire & io.tla.bits.address(5,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
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val isTLReadRxFifo = for( i <- 0 until 2 ) yield { Wire(Bool()) }//io.tla.fire & io.tla.bits.address(5,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
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val isTLReadRxLen = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val isTLReadRxFifo = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val rxLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) }
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val isRxValid = for( i <- 0 until 2 ) yield { rxFifo(i).io.enq.fire }
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val isRxError = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isAxisEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isRxEnd = for( i <- 0 until 2 ) yield { isAxisEnd(i) & ~rxFifo(i).io.deq.valid }
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val intRxError = for( i <- 0 until 2 ) yield { ~RegNext(isRxError(i), false.B) & isRxError(i) }
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val intRxStart = for( i <- 0 until 2 ) yield { rxLen(i) === 0.U & CDRIn(i).io.axis.fire }
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val intRxEnd = for( i <- 0 until 2 ) yield { ~RegNext(isRxEnd(i), false.B) & isRxEnd(i) }
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val rxCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(2.W)) }
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val rxData = for( i <- 0 until 2 ) yield { Reg(UInt(24.W)) }
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val rxLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) }
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val isRxValid = for( i <- 0 until 2 ) yield { rxFifo(i).io.deq.valid }
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val isRxError = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isAxisEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isRxEnd = for( i <- 0 until 2 ) yield { isAxisEnd(i) & ~rxFifo(i).io.deq.valid }
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val intRxError = for( i <- 0 until 2 ) yield { ~RegNext(isRxError(i), false.B) & isRxError(i) }
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val intRxStart = for( i <- 0 until 2 ) yield { rxLen(i) === 0.U & CDRIn(i).io.axis.fire }
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val intRxEnd = for( i <- 0 until 2 ) yield { ~RegNext(isRxEnd(i), false.B) & isRxEnd(i) }
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val intRxFifoEnq = for( i <- 0 until 2 ) yield { rxFifo(i).io.enq.fire }
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val rxCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(2.W)) }
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val rxData = for( i <- 0 until 2 ) yield { Reg(UInt(24.W)) }
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for( i <- 0 until 2 ) {
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when( isTLWriteSoftReset(2+i) ){
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@@ -212,18 +239,18 @@ trait TL2CDRRx{ this: TL2CDRBase =>
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}
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trait TL2CDRIsLast{ this: TL2CDRBase =>
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trait TL2CDRImplIsLast{ this:TL2CDRImplBase =>
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io.isOnline := false.B
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val isReadIsLast = Wire(Bool())//io.tla.fire & io.tla.bits.address(5,0) === "h20".U & io.tla.bits.opcode === 4.U
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val isReadIsLast = Wire(Bool())
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}
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trait TL2CDRUserCRC{ this: TL2CDRBase =>
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trait TL2CDRImplUserCRC{ this: TL2CDRImplBase =>
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val isTLWriteTxFifo: Seq[Bool]
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val isTLReadRxFifo: Seq[Bool]
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val isTLReadTxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } //io.tla.fire & io.tla.bits.address(5,0) === "h24".U & io.tla.bits.opcode === 4.U
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val isTLReadRxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } //io.tla.fire & io.tla.bits.address(5,0) === "h28".U & io.tla.bits.opcode === 4.U
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val isTLReadTxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val isTLReadRxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val txCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) }
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@@ -231,7 +258,7 @@ trait TL2CDRUserCRC{ this: TL2CDRBase =>
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for( i <- 0 until 2 ) {
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txCrc(i).io.enq.valid := isTLWriteTxFifo(i)
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txCrc(i).io.enq.bits := io.tla.bits.data
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txCrc(i).io.enq.bits := bus.a.bits.data
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rxCrc(i).io.enq.valid := isTLReadRxFifo(i)
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rxCrc(i).io.enq.bits := rxFifo(i).io.deq.bits
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@@ -245,12 +272,12 @@ trait TL2CDRUserCRC{ this: TL2CDRBase =>
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}
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trait TL2CDRLimitTimmer{ this: TL2CDRBase =>
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trait TL2CDRImplLimitTimmer{ this: TL2CDRImplBase =>
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val intRxStart: Seq[Bool]
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val isTLWriteSoftReset: Seq[Bool]
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val isTxFifoRelease: Seq[Bool]
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val isTLWriteLimitTimerAim = for( i <- 0 until 2 ) yield { Wire(Bool()) } //io.tla.fire & io.tla.bits.address(5,0) === "h2c".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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val isTLWriteLimitTimerAim = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val isTLWriteLimitTxPair = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val limitTimerCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) }
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@@ -268,7 +295,7 @@ trait TL2CDRLimitTimmer{ this: TL2CDRBase =>
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}
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when( isTLWriteLimitTimerAim(i) ){
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limitTimerAim(i) := io.tla.bits.data
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limitTimerAim(i) := bus.a.bits.data
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}
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when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){
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@@ -280,7 +307,7 @@ trait TL2CDRLimitTimmer{ this: TL2CDRBase =>
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when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){
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txPairSel(i) := i.U
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} .elsewhen( isTLWriteLimitTxPair(i) ){
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txPairSel(i) := io.tla.bits.data
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txPairSel(i) := bus.a.bits.data
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}
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@@ -299,51 +326,57 @@ trait TL2CDRLimitTimmer{ this: TL2CDRBase =>
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class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge)
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with TL2CDRTx with TL2CDRRx
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with TL2CDRIsLast
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with TL2CDRUserCRC
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with TL2CDRLimitTimmer
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class TL2CDRImpl(outer: TL2CDR)(implicit p: Parameters) extends TL2CDRImplBase(outer)
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with TL2CDRImplTx with TL2CDRImplRx
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with TL2CDRImplIsLast
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with TL2CDRImplUserCRC
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with TL2CDRImplLimitTimmer
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{
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isTLWriteSoftReset(0) := io.tla.fire & io.tla.bits.address(5,0) === "h00".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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isTLWriteTxLen(0) := io.tla.fire & io.tla.bits.address(5,0) === "h04".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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isTLWriteTxFifo(0) := io.tla.fire & io.tla.bits.address(5,0) === "h08".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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isTLReadTxCrc(0) := io.tla.fire & io.tla.bits.address(5,0) === "h0c".U & io.tla.bits.opcode === 4.U
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isTLWriteSoftReset(0) := bus.a.fire & bus.a.bits.address(5,0) === "h00".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteTxLen(0) := bus.a.fire & bus.a.bits.address(5,0) === "h04".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteTxFifo(0) := bus.a.fire & bus.a.bits.address(5,0) === "h08".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLReadTxCrc(0) := bus.a.fire & bus.a.bits.address(5,0) === "h0c".U & bus.a.bits.opcode === 4.U
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isTLWriteSoftReset(1) := io.tla.fire & io.tla.bits.address(5,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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isTLWriteTxLen(1) := io.tla.fire & io.tla.bits.address(5,0) === "h14".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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isTLWriteTxFifo(1) := io.tla.fire & io.tla.bits.address(5,0) === "h18".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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isTLReadTxCrc(1) := io.tla.fire & io.tla.bits.address(5,0) === "h1c".U & io.tla.bits.opcode === 4.U
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isTLWriteSoftReset(1) := bus.a.fire & bus.a.bits.address(5,0) === "h10".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteTxLen(1) := bus.a.fire & bus.a.bits.address(5,0) === "h14".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteTxFifo(1) := bus.a.fire & bus.a.bits.address(5,0) === "h18".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLReadTxCrc(1) := bus.a.fire & bus.a.bits.address(5,0) === "h1c".U & bus.a.bits.opcode === 4.U
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isTLWriteSoftReset(2) := io.tla.fire & io.tla.bits.address(5,0) === "h20".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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isTLReadRxLen(0) := io.tla.fire & io.tla.bits.address(5,0) === "h24".U & ( io.tla.bits.opcode === 4.U )
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isTLReadRxFifo(0) := io.tla.fire & io.tla.bits.address(5,0) === "h28".U & ( io.tla.bits.opcode === 4.U )
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isTLReadRxCrc(0) := io.tla.fire & io.tla.bits.address(5,0) === "h2c".U & io.tla.bits.opcode === 4.U
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isTLWriteLimitTimerAim(0) := io.tla.fire & io.tla.bits.address(5,0) === "h30".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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isTLWriteLimitTxPair(0) := io.tla.fire & io.tla.bits.address(5,0) === "h34".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
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isTLWriteSoftReset(2) := bus.a.fire & bus.a.bits.address(5,0) === "h20".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLReadRxLen(0) := bus.a.fire & bus.a.bits.address(5,0) === "h24".U & ( bus.a.bits.opcode === 4.U )
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isTLReadRxFifo(0) := bus.a.fire & bus.a.bits.address(5,0) === "h28".U & ( bus.a.bits.opcode === 4.U )
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isTLReadRxCrc(0) := bus.a.fire & bus.a.bits.address(5,0) === "h2c".U & bus.a.bits.opcode === 4.U
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isTLWriteLimitTimerAim(0) := bus.a.fire & bus.a.bits.address(5,0) === "h30".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteLimitTxPair(0) := bus.a.fire & bus.a.bits.address(5,0) === "h34".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteSoftReset(3) := io.tla.fire & io.tla.bits.address(5,0) === "h40".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
||||
isTLReadRxLen(1) := io.tla.fire & io.tla.bits.address(5,0) === "h44".U & ( io.tla.bits.opcode === 4.U )
|
||||
isTLReadRxFifo(1) := io.tla.fire & io.tla.bits.address(5,0) === "h48".U & ( io.tla.bits.opcode === 4.U )
|
||||
isTLReadRxCrc(1) := io.tla.fire & io.tla.bits.address(5,0) === "h4c".U & io.tla.bits.opcode === 4.U
|
||||
isTLWriteLimitTimerAim(1) := io.tla.fire & io.tla.bits.address(5,0) === "h50".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
||||
isTLWriteLimitTxPair(1) := io.tla.fire & io.tla.bits.address(5,0) === "h54".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
|
||||
isTLWriteSoftReset(3) := bus.a.fire & bus.a.bits.address(5,0) === "h40".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
|
||||
isTLReadRxLen(1) := bus.a.fire & bus.a.bits.address(5,0) === "h44".U & ( bus.a.bits.opcode === 4.U )
|
||||
isTLReadRxFifo(1) := bus.a.fire & bus.a.bits.address(5,0) === "h48".U & ( bus.a.bits.opcode === 4.U )
|
||||
isTLReadRxCrc(1) := bus.a.fire & bus.a.bits.address(5,0) === "h4c".U & bus.a.bits.opcode === 4.U
|
||||
isTLWriteLimitTimerAim(1) := bus.a.fire & bus.a.bits.address(5,0) === "h50".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
|
||||
isTLWriteLimitTxPair(1) := bus.a.fire & bus.a.bits.address(5,0) === "h54".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
|
||||
|
||||
isTLReadStatus := io.tla.fire & io.tla.bits.address(5,0) === "h58".U & ( io.tla.bits.opcode === 4.U )
|
||||
isReadIsLast := io.tla.fire & io.tla.bits.address(5,0) === "h5c".U & ( io.tla.bits.opcode === 4.U )
|
||||
isTLReadStatus := bus.a.fire & bus.a.bits.address(5,0) === "h58".U & ( bus.a.bits.opcode === 4.U )
|
||||
isReadIsLast := bus.a.fire & bus.a.bits.address(5,0) === "h5c".U & ( bus.a.bits.opcode === 4.U )
|
||||
|
||||
io.interrupt(0) := intTxFinish(0)
|
||||
io.interrupt(1) := intTxFinish(1)
|
||||
int(0) := intTxEnd(0)
|
||||
int(1) := intTxEnd(1)
|
||||
|
||||
io.interrupt(2) := intRxError(0)
|
||||
io.interrupt(3) := intRxError(1)
|
||||
int(2) := intRxError(0)
|
||||
int(3) := intRxError(1)
|
||||
|
||||
io.interrupt(4) := intRxStart(0)
|
||||
io.interrupt(5) := intRxStart(1)
|
||||
int(4) := intRxStart(0)
|
||||
int(5) := intRxStart(1)
|
||||
|
||||
io.interrupt(6) := intRxEnd(0)
|
||||
io.interrupt(7) := intRxEnd(1)
|
||||
int(6) := intRxEnd(0)
|
||||
int(7) := intRxEnd(1)
|
||||
|
||||
int(8) := intTxFifoDeq(0)
|
||||
int(9) := intTxFifoDeq(1)
|
||||
|
||||
int(10) := intRxFifoEnq(0)
|
||||
int(11) := intRxFifoEnq(1)
|
||||
|
||||
|
||||
|
||||
@@ -359,37 +392,37 @@ with TL2CDRLimitTimmer
|
||||
|
||||
|
||||
|
||||
io.tla.ready :=
|
||||
bus.a.ready :=
|
||||
tlAReady &
|
||||
MuxCase( true.B, Array(
|
||||
( io.tla.bits.address(5,0) === "h08".U ) -> txFifo(0).io.enq.ready,
|
||||
( io.tla.bits.address(5,0) === "h18".U ) -> txFifo(1).io.enq.ready,
|
||||
( io.tla.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid,
|
||||
( io.tla.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid,
|
||||
( bus.a.bits.address(5,0) === "h08".U ) -> txFifo(0).io.enq.ready,
|
||||
( bus.a.bits.address(5,0) === "h18".U ) -> txFifo(1).io.enq.ready,
|
||||
( bus.a.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid,
|
||||
( bus.a.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid,
|
||||
))
|
||||
|
||||
|
||||
io.tld.valid := tlDValid
|
||||
bus.d.valid := tlDValid
|
||||
|
||||
|
||||
|
||||
|
||||
when( io.tla.fire ) {
|
||||
tlaInfo := io.tla.bits
|
||||
when( bus.a.fire ) {
|
||||
tlaInfo := bus.a.bits
|
||||
}
|
||||
|
||||
when( io.tla.fire ){
|
||||
when( bus.a.fire ){
|
||||
tlAReady := false.B
|
||||
tlDValid := true.B
|
||||
} .elsewhen( io.tld.fire ) {
|
||||
} .elsewhen( bus.d.fire ) {
|
||||
tlAReady := true.B
|
||||
tlDValid := false.B
|
||||
}
|
||||
|
||||
when(isRead) {
|
||||
io.tld.bits := edge.AccessAck(tlaInfo, rdata)
|
||||
bus.d.bits := edge.AccessAck(tlaInfo, rdata)
|
||||
} .otherwise {
|
||||
io.tld.bits := edge.AccessAck(tlaInfo)
|
||||
bus.d.bits := edge.AccessAck(tlaInfo)
|
||||
}
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user