From 55675b93c9b6eb41c25f733518c3e84bde9852b4 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Sat, 8 Feb 2025 16:28:42 +0800 Subject: [PATCH] =?UTF-8?q?txfinish=E8=BD=AC=E6=8D=A2=E4=B8=BAtxfinish?= =?UTF-8?q?=EF=BC=8C=E5=90=8C=E9=A2=91=E6=A8=A1=E5=BC=8F=E6=9C=89=E6=95=88?= =?UTF-8?q?=20=E5=8A=A0=E5=85=A5=E5=8F=91=E9=80=81=E6=8E=A5=E6=94=B6?= =?UTF-8?q?=E4=B8=AD=E6=96=AD=20cdr=E6=A8=A1=E5=9D=97=E4=BE=8B=E5=8C=96?= =?UTF-8?q?=E4=BB=A3=E7=A0=81=E8=A7=84=E8=8C=83=E5=8C=96?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/FSMC.scala.bk | 40 ---- src/main/scala/backBoard/ebus/TL2CDR.scala | 235 +++++++++++--------- 2 files changed, 134 insertions(+), 141 deletions(-) delete mode 100644 src/main/scala/backBoard/ebus/FSMC.scala.bk diff --git a/src/main/scala/backBoard/ebus/FSMC.scala.bk b/src/main/scala/backBoard/ebus/FSMC.scala.bk deleted file mode 100644 index 3bc38eb..0000000 --- a/src/main/scala/backBoard/ebus/FSMC.scala.bk +++ /dev/null @@ -1,40 +0,0 @@ -package BACK - -import chisel3._ -import chisel3.util._ - -import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - - - - -class FSMCMemIO extends Bundle{ - val FSMC = new FSMC_Port_Bundle - - val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle))) - val tld = new DecoupledIO(new TLBundleD(edge.bundle)) -} - -abstract class FSMCMemBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{ - val io: FSMCMemIO = IO(new FSMCMemIO) - - val sram = Module(new ) -} - -trait FSMCMemFSMC{ this: FSMCMemBase => - - -} - -trait FSMCMemTileLink { this: FSMCMemBase => - -} - -class FSMCMem(edge: TLEdgeIn)(implicit p: Parameters) extends FSMCMemBase(edge) -with FSMCMemFSMC -with FSMCMemTileLink -{ - -} diff --git a/src/main/scala/backBoard/ebus/TL2CDR.scala b/src/main/scala/backBoard/ebus/TL2CDR.scala index a02c387..ae7e887 100644 --- a/src/main/scala/backBoard/ebus/TL2CDR.scala +++ b/src/main/scala/backBoard/ebus/TL2CDR.scala @@ -6,35 +6,63 @@ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ -abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record } -abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters -case object BackParamsKey extends Field[BackSetting] +// abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record } +// abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters -case class BackSetting( -){ +// case object BackParamsKey extends Field[BackSetting] -} +// case class BackSetting( +// ){ -trait HasBackParameters { - implicit val p: Parameters +// } - val backSetting = p(BackParamsKey) +// trait HasBackParameters { +// implicit val p: Parameters + +// val backSetting = p(BackParamsKey) +// } + + + +// class BackCfg extends Config((_, _, _) => { +// case BackParamsKey => BackSetting() +// }) + + + +class TL2CDR(implicit p: Parameters) extends LazyModule{ + val device = new SimpleDevice("TL_CDR", Nil) + val node = TLManagerNode(Seq(TLSlavePortParameters.v1( + managers = Seq( + TLSlaveParameters.v2( + address = Seq(AddressSet(0x10000000L, 0xffffL)), //64K + name = Some("TL_CDR"), + regionType = RegionType.VOLATILE, + resources = device.reg, + executable = false, + fifoId = Some(0), + supports = TLMasterToSlaveTransferSizes( + get = TransferSizes(1, 32/8), + putFull = TransferSizes(1, 32/8), + putPartial = TransferSizes(1, 32/8), + ), + ) + ), + beatBytes = 32/8))) + + val int_node = IntSourceNode(IntSourcePortSimple(num = 12, resources = device.int)) + + lazy val module: TL2CDRImpl = new TL2CDRImpl(this) } -class BackCfg extends Config((_, _, _) => { - case BackParamsKey => BackSetting() -}) - - - - -abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule { +abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends LazyModuleImp(outer) { class TLCDRIO extends Bundle{ val overCLK = Input(Bool()) val dDatIn = Input(Bool()) @@ -42,17 +70,15 @@ abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Ba val uDatIn = Input(Bool()) val uDatOut = Output(Bool()) - val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle))) - val tld = new DecoupledIO(new TLBundleD(edge.bundle)) - - val interrupt = Output(Vec(8, Bool())) - val isOnline = Output(Bool()) val isLast = Input(Bool()) } val io: TLCDRIO = IO(new TLCDRIO) + val ( int, _ ) = outer.int_node.out(0) + val ( bus, edge ) = outer.node.in.head + val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } CDRIn(0).io.serDat := io.dDatIn @@ -69,17 +95,17 @@ abstract class TL2CDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Ba val txFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) } val rxFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) } - val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) } //io.tla.fire & io.tla.bits.address(5,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - val isTLReadStatus = Wire( Bool() ) //io.tla.fire & io.tla.bits.address(5,0) === "h0".U & ( io.tla.bits.opcode === 4.U ) + val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) } + val isTLReadStatus = Wire( Bool() ) } -trait TL2CDRTx{ this: TL2CDRBase => +trait TL2CDRImplTx{ this: TL2CDRImplBase => - val isTLWriteTxLen = for( i <- 0 until 2 ) yield { Wire( Bool()) }//io.tla.fire & io.tla.bits.address(5,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - val isTLWriteTxFifo = for( i <- 0 until 2 ) yield { Wire( Bool()) }//io.tla.fire & io.tla.bits.address(5,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + val isTLWriteTxLen = for( i <- 0 until 2 ) yield { Wire( Bool()) } + val isTLWriteTxFifo = for( i <- 0 until 2 ) yield { Wire( Bool()) } val isTxFifoRelease = for( i <- 0 until 2 ) yield { Wire( Bool()) } @@ -88,9 +114,9 @@ trait TL2CDRTx{ this: TL2CDRBase => val isTxFull = for( i <- 0 until 2 ) yield { ~txFifo(i).io.enq.ready } val intTxFifoFull = for( i <- 0 until 2 ) yield { ~RegNext(isTxFull(i), false.B) & isTxFull(i) } val intTxFinish = for( i <- 0 until 2 ) yield { CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast } + val intTxEnd = for( i <- 0 until 2 ) yield { ShiftRegister( intTxFinish(i), 6, false.B, true.B) } - - // val intTxEnd = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B) + val intTxFifoDeq = for( i <- 0 until 2 ) yield { txFifo(i).io.deq.fire } // println("Warning, TxEnd no confident\n") @@ -136,12 +162,12 @@ trait TL2CDRTx{ this: TL2CDRBase => when( isTLWriteTxLen(i) ){ - txLen(i) := io.tla.bits.data + txLen(i) := bus.a.bits.data } .elsewhen( CDROut(i).io.axis.fire ){ txLen(i) := txLen(i) - 1.U } - txFifo(i).io.enq.bits := io.tla.bits.data + txFifo(i).io.enq.bits := bus.a.bits.data txFifo(i).io.enq.valid := isTLWriteTxFifo(i) & txLen(i) =/= 0.U } @@ -150,21 +176,22 @@ trait TL2CDRTx{ this: TL2CDRBase => } -trait TL2CDRRx{ this: TL2CDRBase => +trait TL2CDRImplRx{ this: TL2CDRImplBase => - val isTLReadRxLen = for( i <- 0 until 2 ) yield { Wire(Bool()) }//io.tla.fire & io.tla.bits.address(5,0) === "h18".U & ( io.tla.bits.opcode === 4.U ) - val isTLReadRxFifo = for( i <- 0 until 2 ) yield { Wire(Bool()) }//io.tla.fire & io.tla.bits.address(5,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ) + val isTLReadRxLen = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val isTLReadRxFifo = for( i <- 0 until 2 ) yield { Wire(Bool()) } - val rxLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) } - val isRxValid = for( i <- 0 until 2 ) yield { rxFifo(i).io.enq.fire } - val isRxError = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isAxisEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) } - val isRxEnd = for( i <- 0 until 2 ) yield { isAxisEnd(i) & ~rxFifo(i).io.deq.valid } - val intRxError = for( i <- 0 until 2 ) yield { ~RegNext(isRxError(i), false.B) & isRxError(i) } - val intRxStart = for( i <- 0 until 2 ) yield { rxLen(i) === 0.U & CDRIn(i).io.axis.fire } - val intRxEnd = for( i <- 0 until 2 ) yield { ~RegNext(isRxEnd(i), false.B) & isRxEnd(i) } - val rxCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(2.W)) } - val rxData = for( i <- 0 until 2 ) yield { Reg(UInt(24.W)) } + val rxLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) } + val isRxValid = for( i <- 0 until 2 ) yield { rxFifo(i).io.deq.valid } + val isRxError = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val isAxisEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val isRxEnd = for( i <- 0 until 2 ) yield { isAxisEnd(i) & ~rxFifo(i).io.deq.valid } + val intRxError = for( i <- 0 until 2 ) yield { ~RegNext(isRxError(i), false.B) & isRxError(i) } + val intRxStart = for( i <- 0 until 2 ) yield { rxLen(i) === 0.U & CDRIn(i).io.axis.fire } + val intRxEnd = for( i <- 0 until 2 ) yield { ~RegNext(isRxEnd(i), false.B) & isRxEnd(i) } + val intRxFifoEnq = for( i <- 0 until 2 ) yield { rxFifo(i).io.enq.fire } + val rxCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(2.W)) } + val rxData = for( i <- 0 until 2 ) yield { Reg(UInt(24.W)) } for( i <- 0 until 2 ) { when( isTLWriteSoftReset(2+i) ){ @@ -212,18 +239,18 @@ trait TL2CDRRx{ this: TL2CDRBase => } -trait TL2CDRIsLast{ this: TL2CDRBase => +trait TL2CDRImplIsLast{ this:TL2CDRImplBase => io.isOnline := false.B - val isReadIsLast = Wire(Bool())//io.tla.fire & io.tla.bits.address(5,0) === "h20".U & io.tla.bits.opcode === 4.U + val isReadIsLast = Wire(Bool()) } -trait TL2CDRUserCRC{ this: TL2CDRBase => +trait TL2CDRImplUserCRC{ this: TL2CDRImplBase => val isTLWriteTxFifo: Seq[Bool] val isTLReadRxFifo: Seq[Bool] - val isTLReadTxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } //io.tla.fire & io.tla.bits.address(5,0) === "h24".U & io.tla.bits.opcode === 4.U - val isTLReadRxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } //io.tla.fire & io.tla.bits.address(5,0) === "h28".U & io.tla.bits.opcode === 4.U + val isTLReadTxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } + val isTLReadRxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) } val txCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) } @@ -231,7 +258,7 @@ trait TL2CDRUserCRC{ this: TL2CDRBase => for( i <- 0 until 2 ) { txCrc(i).io.enq.valid := isTLWriteTxFifo(i) - txCrc(i).io.enq.bits := io.tla.bits.data + txCrc(i).io.enq.bits := bus.a.bits.data rxCrc(i).io.enq.valid := isTLReadRxFifo(i) rxCrc(i).io.enq.bits := rxFifo(i).io.deq.bits @@ -245,12 +272,12 @@ trait TL2CDRUserCRC{ this: TL2CDRBase => } -trait TL2CDRLimitTimmer{ this: TL2CDRBase => +trait TL2CDRImplLimitTimmer{ this: TL2CDRImplBase => val intRxStart: Seq[Bool] val isTLWriteSoftReset: Seq[Bool] val isTxFifoRelease: Seq[Bool] - val isTLWriteLimitTimerAim = for( i <- 0 until 2 ) yield { Wire(Bool()) } //io.tla.fire & io.tla.bits.address(5,0) === "h2c".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + val isTLWriteLimitTimerAim = for( i <- 0 until 2 ) yield { Wire(Bool()) } val isTLWriteLimitTxPair = for( i <- 0 until 2 ) yield { Wire(Bool()) } val limitTimerCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) } @@ -268,7 +295,7 @@ trait TL2CDRLimitTimmer{ this: TL2CDRBase => } when( isTLWriteLimitTimerAim(i) ){ - limitTimerAim(i) := io.tla.bits.data + limitTimerAim(i) := bus.a.bits.data } when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ @@ -280,7 +307,7 @@ trait TL2CDRLimitTimmer{ this: TL2CDRBase => when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){ txPairSel(i) := i.U } .elsewhen( isTLWriteLimitTxPair(i) ){ - txPairSel(i) := io.tla.bits.data + txPairSel(i) := bus.a.bits.data } @@ -299,51 +326,57 @@ trait TL2CDRLimitTimmer{ this: TL2CDRBase => -class TL2CDR(edge: TLEdgeIn)(implicit p: Parameters) extends TL2CDRBase(edge) -with TL2CDRTx with TL2CDRRx -with TL2CDRIsLast -with TL2CDRUserCRC -with TL2CDRLimitTimmer +class TL2CDRImpl(outer: TL2CDR)(implicit p: Parameters) extends TL2CDRImplBase(outer) +with TL2CDRImplTx with TL2CDRImplRx +with TL2CDRImplIsLast +with TL2CDRImplUserCRC +with TL2CDRImplLimitTimmer { - isTLWriteSoftReset(0) := io.tla.fire & io.tla.bits.address(5,0) === "h00".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - isTLWriteTxLen(0) := io.tla.fire & io.tla.bits.address(5,0) === "h04".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - isTLWriteTxFifo(0) := io.tla.fire & io.tla.bits.address(5,0) === "h08".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - isTLReadTxCrc(0) := io.tla.fire & io.tla.bits.address(5,0) === "h0c".U & io.tla.bits.opcode === 4.U + isTLWriteSoftReset(0) := bus.a.fire & bus.a.bits.address(5,0) === "h00".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteTxLen(0) := bus.a.fire & bus.a.bits.address(5,0) === "h04".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteTxFifo(0) := bus.a.fire & bus.a.bits.address(5,0) === "h08".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLReadTxCrc(0) := bus.a.fire & bus.a.bits.address(5,0) === "h0c".U & bus.a.bits.opcode === 4.U - isTLWriteSoftReset(1) := io.tla.fire & io.tla.bits.address(5,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - isTLWriteTxLen(1) := io.tla.fire & io.tla.bits.address(5,0) === "h14".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - isTLWriteTxFifo(1) := io.tla.fire & io.tla.bits.address(5,0) === "h18".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - isTLReadTxCrc(1) := io.tla.fire & io.tla.bits.address(5,0) === "h1c".U & io.tla.bits.opcode === 4.U + isTLWriteSoftReset(1) := bus.a.fire & bus.a.bits.address(5,0) === "h10".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteTxLen(1) := bus.a.fire & bus.a.bits.address(5,0) === "h14".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteTxFifo(1) := bus.a.fire & bus.a.bits.address(5,0) === "h18".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLReadTxCrc(1) := bus.a.fire & bus.a.bits.address(5,0) === "h1c".U & bus.a.bits.opcode === 4.U - isTLWriteSoftReset(2) := io.tla.fire & io.tla.bits.address(5,0) === "h20".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - isTLReadRxLen(0) := io.tla.fire & io.tla.bits.address(5,0) === "h24".U & ( io.tla.bits.opcode === 4.U ) - isTLReadRxFifo(0) := io.tla.fire & io.tla.bits.address(5,0) === "h28".U & ( io.tla.bits.opcode === 4.U ) - isTLReadRxCrc(0) := io.tla.fire & io.tla.bits.address(5,0) === "h2c".U & io.tla.bits.opcode === 4.U - isTLWriteLimitTimerAim(0) := io.tla.fire & io.tla.bits.address(5,0) === "h30".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - isTLWriteLimitTxPair(0) := io.tla.fire & io.tla.bits.address(5,0) === "h34".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + isTLWriteSoftReset(2) := bus.a.fire & bus.a.bits.address(5,0) === "h20".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLReadRxLen(0) := bus.a.fire & bus.a.bits.address(5,0) === "h24".U & ( bus.a.bits.opcode === 4.U ) + isTLReadRxFifo(0) := bus.a.fire & bus.a.bits.address(5,0) === "h28".U & ( bus.a.bits.opcode === 4.U ) + isTLReadRxCrc(0) := bus.a.fire & bus.a.bits.address(5,0) === "h2c".U & bus.a.bits.opcode === 4.U + isTLWriteLimitTimerAim(0) := bus.a.fire & bus.a.bits.address(5,0) === "h30".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteLimitTxPair(0) := bus.a.fire & bus.a.bits.address(5,0) === "h34".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLWriteSoftReset(3) := io.tla.fire & io.tla.bits.address(5,0) === "h40".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - isTLReadRxLen(1) := io.tla.fire & io.tla.bits.address(5,0) === "h44".U & ( io.tla.bits.opcode === 4.U ) - isTLReadRxFifo(1) := io.tla.fire & io.tla.bits.address(5,0) === "h48".U & ( io.tla.bits.opcode === 4.U ) - isTLReadRxCrc(1) := io.tla.fire & io.tla.bits.address(5,0) === "h4c".U & io.tla.bits.opcode === 4.U - isTLWriteLimitTimerAim(1) := io.tla.fire & io.tla.bits.address(5,0) === "h50".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - isTLWriteLimitTxPair(1) := io.tla.fire & io.tla.bits.address(5,0) === "h54".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + isTLWriteSoftReset(3) := bus.a.fire & bus.a.bits.address(5,0) === "h40".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLReadRxLen(1) := bus.a.fire & bus.a.bits.address(5,0) === "h44".U & ( bus.a.bits.opcode === 4.U ) + isTLReadRxFifo(1) := bus.a.fire & bus.a.bits.address(5,0) === "h48".U & ( bus.a.bits.opcode === 4.U ) + isTLReadRxCrc(1) := bus.a.fire & bus.a.bits.address(5,0) === "h4c".U & bus.a.bits.opcode === 4.U + isTLWriteLimitTimerAim(1) := bus.a.fire & bus.a.bits.address(5,0) === "h50".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) + isTLWriteLimitTxPair(1) := bus.a.fire & bus.a.bits.address(5,0) === "h54".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) ) - isTLReadStatus := io.tla.fire & io.tla.bits.address(5,0) === "h58".U & ( io.tla.bits.opcode === 4.U ) - isReadIsLast := io.tla.fire & io.tla.bits.address(5,0) === "h5c".U & ( io.tla.bits.opcode === 4.U ) + isTLReadStatus := bus.a.fire & bus.a.bits.address(5,0) === "h58".U & ( bus.a.bits.opcode === 4.U ) + isReadIsLast := bus.a.fire & bus.a.bits.address(5,0) === "h5c".U & ( bus.a.bits.opcode === 4.U ) - io.interrupt(0) := intTxFinish(0) - io.interrupt(1) := intTxFinish(1) + int(0) := intTxEnd(0) + int(1) := intTxEnd(1) - io.interrupt(2) := intRxError(0) - io.interrupt(3) := intRxError(1) + int(2) := intRxError(0) + int(3) := intRxError(1) - io.interrupt(4) := intRxStart(0) - io.interrupt(5) := intRxStart(1) + int(4) := intRxStart(0) + int(5) := intRxStart(1) - io.interrupt(6) := intRxEnd(0) - io.interrupt(7) := intRxEnd(1) + int(6) := intRxEnd(0) + int(7) := intRxEnd(1) + + int(8) := intTxFifoDeq(0) + int(9) := intTxFifoDeq(1) + + int(10) := intRxFifoEnq(0) + int(11) := intRxFifoEnq(1) @@ -359,37 +392,37 @@ with TL2CDRLimitTimmer - io.tla.ready := + bus.a.ready := tlAReady & MuxCase( true.B, Array( - ( io.tla.bits.address(5,0) === "h08".U ) -> txFifo(0).io.enq.ready, - ( io.tla.bits.address(5,0) === "h18".U ) -> txFifo(1).io.enq.ready, - ( io.tla.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid, - ( io.tla.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid, + ( bus.a.bits.address(5,0) === "h08".U ) -> txFifo(0).io.enq.ready, + ( bus.a.bits.address(5,0) === "h18".U ) -> txFifo(1).io.enq.ready, + ( bus.a.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid, + ( bus.a.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid, )) - io.tld.valid := tlDValid + bus.d.valid := tlDValid - when( io.tla.fire ) { - tlaInfo := io.tla.bits + when( bus.a.fire ) { + tlaInfo := bus.a.bits } - when( io.tla.fire ){ + when( bus.a.fire ){ tlAReady := false.B tlDValid := true.B - } .elsewhen( io.tld.fire ) { + } .elsewhen( bus.d.fire ) { tlAReady := true.B tlDValid := false.B } when(isRead) { - io.tld.bits := edge.AccessAck(tlaInfo, rdata) + bus.d.bits := edge.AccessAck(tlaInfo, rdata) } .otherwise { - io.tld.bits := edge.AccessAck(tlaInfo) + bus.d.bits := edge.AccessAck(tlaInfo) }