454 lines
15 KiB
Scala
454 lines
15 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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// abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
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// abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
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// case object BackParamsKey extends Field[BackSetting]
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// case class BackSetting(
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// ){
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// }
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// trait HasBackParameters {
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// implicit val p: Parameters
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// val backSetting = p(BackParamsKey)
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// }
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// class BackCfg extends Config((_, _, _) => {
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// case BackParamsKey => BackSetting()
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// })
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class TL2CDR(implicit p: Parameters) extends LazyModule{
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val device = new SimpleDevice("TL_CDR", Nil)
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val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
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managers = Seq(
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TLSlaveParameters.v2(
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address = Seq(AddressSet(0x10000000L, 0xffffL)), //64K
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name = Some("TL_CDR"),
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regionType = RegionType.VOLATILE,
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resources = device.reg,
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executable = false,
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fifoId = Some(0),
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supports = TLMasterToSlaveTransferSizes(
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get = TransferSizes(1, 32/8),
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putFull = TransferSizes(1, 32/8),
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putPartial = TransferSizes(1, 32/8),
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),
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)
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),
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beatBytes = 32/8)))
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val int_node = IntSourceNode(IntSourcePortSimple(num = 12, resources = device.int))
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lazy val module: TL2CDRImpl = new TL2CDRImpl(this)
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}
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abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends LazyModuleImp(outer) {
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class TLCDRIO extends Bundle{
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val overCLK = Input(Bool())
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val dDatIn = Input(Bool())
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val dDatOut = Output(Bool())
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val uDatIn = Input(Bool())
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val uDatOut = Output(Bool())
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val isOnline = Output(Bool())
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val isLast = Input(Bool())
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}
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val io: TLCDRIO = IO(new TLCDRIO)
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val ( int, _ ) = outer.int_node.out(0)
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val ( bus, edge ) = outer.node.in.head
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val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
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CDRIn(0).io.serDat := io.dDatIn
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CDRIn(1).io.serDat := io.uDatIn
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CDRIn(0).io.overCLK := io.overCLK
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CDRIn(1).io.overCLK := io.overCLK
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val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
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io.dDatOut := CDROut(0).io.serDat
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io.uDatOut := CDROut(1).io.serDat
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val txFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) }
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val rxFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) }
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val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) }
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val isTLReadStatus = Wire( Bool() )
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}
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trait TL2CDRImplTx{ this: TL2CDRImplBase =>
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val isTLWriteTxLen = for( i <- 0 until 2 ) yield { Wire( Bool()) }
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val isTLWriteTxFifo = for( i <- 0 until 2 ) yield { Wire( Bool()) }
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val isTxFifoRelease = for( i <- 0 until 2 ) yield { Wire( Bool()) }
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val txLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) }
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val isTxBusy = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isTxFull = for( i <- 0 until 2 ) yield { ~txFifo(i).io.enq.ready }
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val intTxFifoFull = for( i <- 0 until 2 ) yield { ~RegNext(isTxFull(i), false.B) & isTxFull(i) }
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val intTxFinish = for( i <- 0 until 2 ) yield { CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast }
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val intTxEnd = for( i <- 0 until 2 ) yield { ShiftRegister( intTxFinish(i), 6, false.B, true.B) }
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val intTxFifoDeq = for( i <- 0 until 2 ) yield { txFifo(i).io.deq.fire }
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// println("Warning, TxEnd no confident\n")
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val txCnt = for( i <- 0 until 2 ) yield { Reg(UInt(2.W)) }
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val txData = for( i <- 0 until 2 ) yield { Reg(UInt(32.W)) }
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for( i <- 0 until 2 ) {
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when( txFifo(i).io.deq.fire ){ //txCnt(i) === 3.U
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txData(i) := txFifo(i).io.deq.bits
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when( isTxBusy(i) ){
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assert(CDROut(i).io.axis.fire)
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}
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} .elsewhen( CDROut(i).io.axis.fire ){
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txData(i) := txData(i) << 8
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}
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txFifo(i).io.deq.ready :=
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isTxFifoRelease(i) & Mux( isTxBusy(i), CDROut(i).io.axis.fire & txCnt(i) === 3.U, true.B )
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txFifo(i).reset := reset.asBool | isTLWriteSoftReset(0+i)
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CDROut(i).reset := reset.asBool | isTLWriteSoftReset(0+i)
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CDROut(i).io.axis.bits.tdata := txData(i).head(8)
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CDROut(i).io.axis.bits.tlast := ~txFifo(i).io.deq.valid & txCnt(i) === 3.U
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CDROut(i).io.axis.bits.tuser := false.B
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CDROut(i).io.axis.valid := isTxBusy(i)
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when( isTLWriteSoftReset(i) ){
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isTxBusy(i) := false.B
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}.elsewhen( txFifo(i).io.deq.fire & ~isTxBusy(i) ){
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isTxBusy(i) := true.B
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} .elsewhen( CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast ){
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isTxBusy(i) := false.B
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}
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when( isTLWriteSoftReset(0+i) ){
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txCnt(i) := 0.U
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} .elsewhen( CDROut(i).io.axis.fire ){
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txCnt(i) := txCnt(i) + 1.U
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}
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when( isTLWriteTxLen(i) ){
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txLen(i) := bus.a.bits.data
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} .elsewhen( CDROut(i).io.axis.fire ){
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txLen(i) := txLen(i) - 1.U
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}
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txFifo(i).io.enq.bits := bus.a.bits.data
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txFifo(i).io.enq.valid := isTLWriteTxFifo(i) & txLen(i) =/= 0.U
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}
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}
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trait TL2CDRImplRx{ this: TL2CDRImplBase =>
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val isTLReadRxLen = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val isTLReadRxFifo = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val rxLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) }
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val isRxValid = for( i <- 0 until 2 ) yield { rxFifo(i).io.deq.valid }
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val isRxError = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isAxisEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isRxEnd = for( i <- 0 until 2 ) yield { isAxisEnd(i) & ~rxFifo(i).io.deq.valid }
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val intRxError = for( i <- 0 until 2 ) yield { ~RegNext(isRxError(i), false.B) & isRxError(i) }
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val intRxStart = for( i <- 0 until 2 ) yield { rxLen(i) === 0.U & CDRIn(i).io.axis.fire }
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val intRxEnd = for( i <- 0 until 2 ) yield { ~RegNext(isRxEnd(i), false.B) & isRxEnd(i) }
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val intRxFifoEnq = for( i <- 0 until 2 ) yield { rxFifo(i).io.enq.fire }
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val rxCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(2.W)) }
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val rxData = for( i <- 0 until 2 ) yield { Reg(UInt(24.W)) }
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for( i <- 0 until 2 ) {
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when( isTLWriteSoftReset(2+i) ){
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isAxisEnd(i) := false.B
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} .elsewhen( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast ){
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isAxisEnd(i) := true.B
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}
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when( isTLWriteSoftReset(2+i) ){
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rxCnt(i) := 0.U
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} .elsewhen( CDRIn(i).io.axis.fire ){
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rxCnt(i) := rxCnt(i) + 1.U
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rxData(i) := Cat( rxData(i), CDRIn(i).io.axis.bits.tdata )
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}
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when( isTLWriteSoftReset(2+i) ){
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rxLen(i) := 0.U
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} .elsewhen( CDRIn(i).io.axis.fire ){
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rxLen(i) := rxLen(i) + 1.U
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}
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rxFifo(i).io.enq.valid := CDRIn(i).io.axis.fire & rxCnt(i) === 3.U
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rxFifo(i).io.enq.bits := Cat( rxData(i)(23, 0) , CDRIn(i).io.axis.bits.tdata )
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assert( ~(( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast) & rxCnt(i) =/= 3.U), "Assert Failed! Rx must 4-byte Align!" )
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CDRIn(i).io.axis.ready := true.B
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rxFifo(i).reset := reset.asBool | isTLWriteSoftReset(2+i)
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CDRIn(i).reset := reset.asBool | isTLWriteSoftReset(2+i)
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rxFifo(i).io.deq.ready := isTLReadRxFifo(i)
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when( isTLWriteSoftReset(2+i) ){
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isRxError(i) := false.B
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} .elsewhen( rxFifo(i).io.enq.valid & ~rxFifo(i).io.enq.ready ){
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isRxError(i) := true.B
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printf(s"Warning, RxFifo$i Overflow!\n")
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}
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}
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}
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trait TL2CDRImplIsLast{ this:TL2CDRImplBase =>
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io.isOnline := false.B
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val isReadIsLast = Wire(Bool())
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}
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trait TL2CDRImplUserCRC{ this: TL2CDRImplBase =>
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val isTLWriteTxFifo: Seq[Bool]
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val isTLReadRxFifo: Seq[Bool]
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val isTLReadTxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val isTLReadRxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val txCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) }
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val rxCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) }
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for( i <- 0 until 2 ) {
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txCrc(i).io.enq.valid := isTLWriteTxFifo(i)
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txCrc(i).io.enq.bits := bus.a.bits.data
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rxCrc(i).io.enq.valid := isTLReadRxFifo(i)
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rxCrc(i).io.enq.bits := rxFifo(i).io.deq.bits
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txCrc(i).reset := reset.asBool | isTLWriteSoftReset(0+i)
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rxCrc(i).reset := reset.asBool | isTLWriteSoftReset(2+i)
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}
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}
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trait TL2CDRImplLimitTimmer{ this: TL2CDRImplBase =>
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val intRxStart: Seq[Bool]
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val isTLWriteSoftReset: Seq[Bool]
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val isTxFifoRelease: Seq[Bool]
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val isTLWriteLimitTimerAim = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val isTLWriteLimitTxPair = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val limitTimerCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) }
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val limitTimerAim = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) }
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val isLimitTimerTrigger = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val txPairSel = for( i <- 0 until 2 ) yield { RegInit((i.U)(2.W)) }
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for( i <- 0 until 2 ){
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when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){
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limitTimerCnt(i) := 0.U
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} .elsewhen( limitTimerCnt(i) =/= limitTimerAim(i) ){
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when( isLimitTimerTrigger(i) ){
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limitTimerCnt(i) := limitTimerCnt(i) + 1.U
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}
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}
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when( isTLWriteLimitTimerAim(i) ){
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limitTimerAim(i) := bus.a.bits.data
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}
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when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){
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isLimitTimerTrigger(i) := false.B
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} .elsewhen( intRxStart(i) ){
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isLimitTimerTrigger(i) := true.B
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}
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when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){
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txPairSel(i) := i.U
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} .elsewhen( isTLWriteLimitTxPair(i) ){
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txPairSel(i) := bus.a.bits.data
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}
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isTxFifoRelease(i) := ( 0 until 2).map{ lmt =>
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((txPairSel(lmt) =/= i.U) | (limitTimerCnt(lmt) === limitTimerAim(lmt)))
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}.reduce(_&_)
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}
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}
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class TL2CDRImpl(outer: TL2CDR)(implicit p: Parameters) extends TL2CDRImplBase(outer)
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with TL2CDRImplTx with TL2CDRImplRx
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with TL2CDRImplIsLast
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with TL2CDRImplUserCRC
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with TL2CDRImplLimitTimmer
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{
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isTLWriteSoftReset(0) := bus.a.fire & bus.a.bits.address(5,0) === "h00".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteTxLen(0) := bus.a.fire & bus.a.bits.address(5,0) === "h04".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteTxFifo(0) := bus.a.fire & bus.a.bits.address(5,0) === "h08".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLReadTxCrc(0) := bus.a.fire & bus.a.bits.address(5,0) === "h0c".U & bus.a.bits.opcode === 4.U
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isTLWriteSoftReset(1) := bus.a.fire & bus.a.bits.address(5,0) === "h10".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteTxLen(1) := bus.a.fire & bus.a.bits.address(5,0) === "h14".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteTxFifo(1) := bus.a.fire & bus.a.bits.address(5,0) === "h18".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLReadTxCrc(1) := bus.a.fire & bus.a.bits.address(5,0) === "h1c".U & bus.a.bits.opcode === 4.U
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isTLWriteSoftReset(2) := bus.a.fire & bus.a.bits.address(5,0) === "h20".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLReadRxLen(0) := bus.a.fire & bus.a.bits.address(5,0) === "h24".U & ( bus.a.bits.opcode === 4.U )
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isTLReadRxFifo(0) := bus.a.fire & bus.a.bits.address(5,0) === "h28".U & ( bus.a.bits.opcode === 4.U )
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isTLReadRxCrc(0) := bus.a.fire & bus.a.bits.address(5,0) === "h2c".U & bus.a.bits.opcode === 4.U
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isTLWriteLimitTimerAim(0) := bus.a.fire & bus.a.bits.address(5,0) === "h30".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteLimitTxPair(0) := bus.a.fire & bus.a.bits.address(5,0) === "h34".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteSoftReset(3) := bus.a.fire & bus.a.bits.address(5,0) === "h40".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLReadRxLen(1) := bus.a.fire & bus.a.bits.address(5,0) === "h44".U & ( bus.a.bits.opcode === 4.U )
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isTLReadRxFifo(1) := bus.a.fire & bus.a.bits.address(5,0) === "h48".U & ( bus.a.bits.opcode === 4.U )
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isTLReadRxCrc(1) := bus.a.fire & bus.a.bits.address(5,0) === "h4c".U & bus.a.bits.opcode === 4.U
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isTLWriteLimitTimerAim(1) := bus.a.fire & bus.a.bits.address(5,0) === "h50".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLWriteLimitTxPair(1) := bus.a.fire & bus.a.bits.address(5,0) === "h54".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
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isTLReadStatus := bus.a.fire & bus.a.bits.address(5,0) === "h58".U & ( bus.a.bits.opcode === 4.U )
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isReadIsLast := bus.a.fire & bus.a.bits.address(5,0) === "h5c".U & ( bus.a.bits.opcode === 4.U )
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int(0) := intTxEnd(0)
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int(1) := intTxEnd(1)
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int(2) := intRxError(0)
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int(3) := intRxError(1)
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int(4) := intRxStart(0)
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int(5) := intRxStart(1)
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int(6) := intRxEnd(0)
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int(7) := intRxEnd(1)
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int(8) := intTxFifoDeq(0)
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int(9) := intTxFifoDeq(1)
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int(10) := intRxFifoEnq(0)
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int(11) := intRxFifoEnq(1)
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val tlaInfo = Reg(new TLBundleA(edge.bundle))
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val rdata = Reg(UInt(32.W))
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val tlAReady = RegInit(true.B)
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val tlDValid = RegInit(false.B)
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val isRead = tlaInfo.opcode === 4.U
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bus.a.ready :=
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tlAReady &
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MuxCase( true.B, Array(
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( bus.a.bits.address(5,0) === "h08".U ) -> txFifo(0).io.enq.ready,
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( bus.a.bits.address(5,0) === "h18".U ) -> txFifo(1).io.enq.ready,
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( bus.a.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid,
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( bus.a.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid,
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))
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|
|
|
|
bus.d.valid := tlDValid
|
|
|
|
|
|
|
|
|
|
when( bus.a.fire ) {
|
|
tlaInfo := bus.a.bits
|
|
}
|
|
|
|
when( bus.a.fire ){
|
|
tlAReady := false.B
|
|
tlDValid := true.B
|
|
} .elsewhen( bus.d.fire ) {
|
|
tlAReady := true.B
|
|
tlDValid := false.B
|
|
}
|
|
|
|
when(isRead) {
|
|
bus.d.bits := edge.AccessAck(tlaInfo, rdata)
|
|
} .otherwise {
|
|
bus.d.bits := edge.AccessAck(tlaInfo)
|
|
}
|
|
|
|
|
|
when( isTLReadStatus ){
|
|
rdata := Cat( isRxValid(1), isRxValid(0), isRxError(1), isRxError(0), isTxBusy(1), isTxBusy(0), isTxFull(1), isTxFull(0) )
|
|
} .elsewhen(isTLReadRxLen(0) ){
|
|
rdata := rxLen(0)
|
|
} .elsewhen(isTLReadRxLen(1) ){
|
|
rdata := rxLen(1)
|
|
} .elsewhen(isTLReadRxFifo(0) ){
|
|
rdata := rxFifo(0).io.deq.bits
|
|
} .elsewhen(isTLReadRxFifo(1) ){
|
|
rdata := rxFifo(1).io.deq.bits
|
|
} .elsewhen(isReadIsLast){
|
|
rdata := io.isLast
|
|
} .elsewhen(isTLReadTxCrc(0)){
|
|
rdata := txCrc(0).io.crc
|
|
} .elsewhen(isTLReadTxCrc(1)){
|
|
rdata := txCrc(1).io.crc
|
|
} .elsewhen(isTLReadRxCrc(0)){
|
|
rdata := rxCrc(0).io.crc
|
|
} .elsewhen(isTLReadRxCrc(1)){
|
|
rdata := rxCrc(1).io.crc
|
|
}
|
|
|
|
}
|
|
|
|
|