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fix sync misunderstanding

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RuigeLee
2023-09-11 17:39:19 +08:00
parent 05a905ac39
commit 527f6bd761
1 changed files with 9 additions and 9 deletions
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16
src/main/scala/backBoard/MirrorSRAM.scala
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@@ -219,15 +219,15 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
| reg [15:0] ram[0:511];
| reg [15:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| if( addrw[0] ) begin
| ram[addrw[9:1]] <= #1 { dataw, ram[addrw[9:1]][7:0] };
| end else begin
| ram[addrw[9:1]] <= #1 { ram[addrw[9:1]][15:8], dataw };
| end
| end
| always @(posedge clockw) begin
| if(enw) begin
| if( addrw[0] ) begin
| ram[addrw[9:1]][15:8] <= #1 dataw;
| end else begin
| ram[addrw[9:1]][7:0] <= #1 dataw;
| end
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin