diff --git a/src/main/scala/backBoard/MirrorSRAM.scala b/src/main/scala/backBoard/MirrorSRAM.scala
index 2a6d4de..77b627b 100644
--- a/src/main/scala/backBoard/MirrorSRAM.scala
+++ b/src/main/scala/backBoard/MirrorSRAM.scala
@@ -219,15 +219,15 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
       |  	reg [15:0] ram[0:511];
       |  	reg [15:0] data_r_reg;
       |  
-      |  			always @(posedge clockw) begin
-      |  				if(enw) begin
-      |           if( addrw[0] ) begin
-      |             ram[addrw[9:1]] <= #1 { dataw, ram[addrw[9:1]][7:0] };
-      |           end else begin
-      |             ram[addrw[9:1]] <= #1 { ram[addrw[9:1]][15:8], dataw };
-      |           end				
-      |  				end
-      |       end
+  		|   always @(posedge clockw) begin
+  		|     if(enw) begin
+      |       if( addrw[0] ) begin
+      |         ram[addrw[9:1]][15:8] <= #1 dataw;
+      |       end else begin
+      |         ram[addrw[9:1]][7:0]  <= #1 dataw;
+      |       end				
+  		|   	end
+      |   end
       |  
       |       always @(posedge clockr) begin
       |  				if(enr) begin