From 527f6bd76159e1577c338c560de2c6af8bf12c1c Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Mon, 11 Sep 2023 17:39:19 +0800 Subject: [PATCH] fix sync misunderstanding --- src/main/scala/backBoard/MirrorSRAM.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/main/scala/backBoard/MirrorSRAM.scala b/src/main/scala/backBoard/MirrorSRAM.scala index 2a6d4de..77b627b 100644 --- a/src/main/scala/backBoard/MirrorSRAM.scala +++ b/src/main/scala/backBoard/MirrorSRAM.scala @@ -219,15 +219,15 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline { | reg [15:0] ram[0:511]; | reg [15:0] data_r_reg; | - | always @(posedge clockw) begin - | if(enw) begin - | if( addrw[0] ) begin - | ram[addrw[9:1]] <= #1 { dataw, ram[addrw[9:1]][7:0] }; - | end else begin - | ram[addrw[9:1]] <= #1 { ram[addrw[9:1]][15:8], dataw }; - | end - | end - | end + | always @(posedge clockw) begin + | if(enw) begin + | if( addrw[0] ) begin + | ram[addrw[9:1]][15:8] <= #1 dataw; + | end else begin + | ram[addrw[9:1]][7:0] <= #1 dataw; + | end + | end + | end | | always @(posedge clockr) begin | if(enr) begin