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fix sync misunderstanding

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RuigeLee
2023-09-11 17:39:19 +08:00
parent 05a905ac39
commit 527f6bd761
1 changed files with 9 additions and 9 deletions
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4
src/main/scala/backBoard/MirrorSRAM.scala
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@@ -222,9 +222,9 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
| always @(posedge clockw) begin | always @(posedge clockw) begin
| if(enw) begin | if(enw) begin
| if( addrw[0] ) begin | if( addrw[0] ) begin
| ram[addrw[9:1]] <= #1 { dataw, ram[addrw[9:1]][7:0] }; | ram[addrw[9:1]][15:8] <= #1 dataw;
| end else begin | end else begin
| ram[addrw[9:1]] <= #1 { ram[addrw[9:1]][15:8], dataw }; | ram[addrw[9:1]][7:0] <= #1 dataw;
| end | end
| end | end
| end | end