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缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口

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This commit is contained in:
RuigeLee
2024-10-31 17:38:12 +08:00
parent 20a52f2506
commit 46882b6b4d
4 changed files with 77 additions and 81 deletions
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28
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -57,7 +57,7 @@ trait CDRInOverSample{ this: CDRInBase =>
// (sampleReg(2) & sampleReg(1) & sampleReg(0)) // (sampleReg(2) & sampleReg(1) & sampleReg(0))
val syncSerDat = ShiftRegister( val syncSerDat = ShiftRegister(
Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } ) PriorityMux( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
, 2 ) , 2 )
} }
@@ -66,8 +66,8 @@ trait CDRInAxis{ this: CDRInBase =>
def HeaderByte: Int = 8 def HeaderByte: Int = 8
val ETH_PRE = "h55".U val ETH_PRE = "h55".U(8.W)
val ETH_SFD = "hD5".U val ETH_SFD = "hD5".U(8.W)
val STATE_IDLE = 0.U val STATE_IDLE = 0.U
val STATE_HEADER = 1.U val STATE_HEADER = 1.U
@@ -85,22 +85,20 @@ trait CDRInAxis{ this: CDRInBase =>
val crcCmp = Reg(UInt(32.W)) val crcCmp = Reg(UInt(32.W))
val bitCnt = Reg(UInt(3.W)) val bitCnt = Reg(UInt(3.W))
val byteCnt = RegInit(0.U(16.W)) val byteCnt = RegInit(0.U(12.W))
val syncSerDat: Bool val syncSerDat: Bool
val shiftData = RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat) val checkSFD = RegInit( 0.U(16.W) ); checkSFD := Cat( checkSFD(14,0), syncSerDat )
val header = Reg(UInt((8*HeaderByte).W)) val shiftData = checkSFD(7,0) //RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat)
val payloadLen = header(63,52)
val operation = header(51,48) val payloadLen = RegEnable( shiftData, byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER )
val param = header(47, 0)
val isArbLock: Bool val isArbLock: Bool
val checkSFD = ShiftRegister( shiftData, 8 )
stateNext := stateNext :=
Mux1H(Seq( Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( isArbLock & checkSFD === ETH_PRE & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE (stateCurr === STATE_IDLE) -> ( Mux( isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ), (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD
(stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC (stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
@@ -110,13 +108,13 @@ trait CDRInAxis{ this: CDRInBase =>
when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock & checkSFD === ETH_PRE ){ //first align when( stateCurr === STATE_IDLE & isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD) ){ //first align
bitCnt := 0.U bitCnt := 0.U
} .otherwise{ } .otherwise{
bitCnt := bitCnt + 1.U bitCnt := bitCnt + 1.U
} }
when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock & checkSFD === ETH_PRE ){ //first align when( stateCurr === STATE_IDLE & isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD) ){ //first align
byteCnt := 0.U byteCnt := 0.U
} .elsewhen( bitCnt === 7.U ){ } .elsewhen( bitCnt === 7.U ){
when( stateCurr === STATE_HEADER ){ when( stateCurr === STATE_HEADER ){
@@ -131,9 +129,7 @@ trait CDRInAxis{ this: CDRInBase =>
} }
} }
when( stateCurr === STATE_HEADER & bitCnt === 7.U ){
header := Cat( header( 8*HeaderByte-1-8, 0), shiftData )
}

6
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -36,7 +36,7 @@ class CDROut extends Module{
val bitCnt = Reg(UInt(3.W)) val bitCnt = Reg(UInt(3.W))
val byteCnt = Reg(UInt(16.W)) val byteCnt = Reg(UInt(3.W)) //payload dont need to count
val crcOut = crcUnit.io.crc val crcOut = crcUnit.io.crc
val reset_crc = stateCurr === STATE_IDLE val reset_crc = stateCurr === STATE_IDLE
@@ -77,7 +77,7 @@ class CDROut extends Module{
} .elsewhen( stateCurr === STATE_PAYLOAD ){ } .elsewhen( stateCurr === STATE_PAYLOAD ){
shiftData := io.axis.bits.tdata shiftData := io.axis.bits.tdata
} .elsewhen( stateCurr === STATE_FCS ){ } .elsewhen( stateCurr === STATE_FCS ){
shiftData := Mux1H(Seq( shiftData := PriorityMux(Seq(
( byteCnt === 0.U) -> ~crcOut( 7,0), ( byteCnt === 0.U) -> ~crcOut( 7,0),
( byteCnt === 1.U) -> ~crcOut(15,8), ( byteCnt === 1.U) -> ~crcOut(15,8),
( byteCnt === 2.U) -> ~crcOut(23,16), ( byteCnt === 2.U) -> ~crcOut(23,16),
@@ -94,7 +94,7 @@ class CDROut extends Module{
bitCnt := bitCnt + 1.U bitCnt := bitCnt + 1.U
} }
when( stateNext =/= stateCurr ){ when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
byteCnt := 0.U byteCnt := 0.U
} .elsewhen( bitCnt === 7.U ){ } .elsewhen( bitCnt === 7.U ){
byteCnt := byteCnt + 1.U byteCnt := byteCnt + 1.U

4
src/main/scala/backBoard/pico/BackSystem.scala
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@@ -92,7 +92,9 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
)), )),
beatBytes = 32/8))) beatBytes = 32/8)))
val xbar = TLXbar() val xbar = TLXbar(
//policy = TLArbiter.lowestIndexFirst
)
xbar := coreClientNode xbar := coreClientNode
cdrNode := xbar cdrNode := xbar
sram.node := xbar sram.node := xbar

120
src/main/scala/backBoard/pico/TLCDR.scala
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@@ -39,21 +39,20 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
// CDROut.io.axis = Flipped(Decoupled(new AXIS_Bundle(8))) // CDROut.io.axis = Flipped(Decoupled(new AXIS_Bundle(8)))
val txFifo = Module(new Queue(UInt(32.W), 8)) val txFifo = Module(new Queue(UInt(32.W), 4))
val rxFifo = Module(new Queue(UInt(32.W), 8)) val rxFifo = Module(new Queue(UInt(32.W), 4))
} }
trait TLCDRTx{ this: TLCDRBase => trait TLCDRTx{ this: TLCDRBase =>
val isTLReadTxStatus = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( io.tla.bits.opcode === 4.U ) val isTLReadStatus = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(6,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxSoftReset = isTLWriteTxLen
val txLen = RegInit(0.U(32.W)) val txLen = RegInit(0.U(12.W))
val isTxBusy = RegInit(false.B) val isTxBusy = RegInit(false.B)
val isTxFull = ~txFifo.io.enq.ready val isTxFull = ~txFifo.io.enq.ready
val isTxError = RegInit(false.B) val isTxError = RegInit(false.B)
@@ -64,18 +63,28 @@ trait TLCDRTx{ this: TLCDRBase =>
val txCnt = Reg(UInt(2.W)) val txCnt = Reg(UInt(2.W))
val txData = RegEnable( txFifo.io.deq.bits, txFifo.io.deq.fire) val txData = Reg(UInt(32.W))
when( txFifo.io.deq.fire ){ //txCnt === 3.U
txData := txFifo.io.deq.bits
assert(CDROut.io.axis.fire)
} .elsewhen( CDROut.io.axis.fire ){
txData := txData << 8
}
txFifo.io.deq.ready := txFifo.io.deq.ready :=
Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B ) Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B )
txFifo.reset := reset.asBool | isTLWriteTxLen txFifo.reset := reset.asBool | isTLWriteTxLen
CDROut.io.axis.bits.tdata := Mux1H(Seq( CDROut.io.axis.bits.tdata := txData.head(8)
(txCnt === 0.U) -> txData(31, 24),
(txCnt === 1.U) -> txData(23, 16), // PriorityMux(Seq(
(txCnt === 2.U) -> txData(15, 8), // (txCnt === 0.U) -> txData(31, 24),
(txCnt === 3.U) -> txData( 7, 0), // (txCnt === 1.U) -> txData(23, 16),
)) // (txCnt === 2.U) -> txData(15, 8),
// (txCnt === 3.U) -> txData( 7, 0),
// ))
CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U
CDROut.io.axis.bits.tuser := isTxError CDROut.io.axis.bits.tuser := isTxError
@@ -107,7 +116,7 @@ trait TLCDRTx{ this: TLCDRBase =>
txFifo.io.enq.bits := io.tla.bits.data txFifo.io.enq.bits := io.tla.bits.data
txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U
when( isTLReadTxStatus | isTLWriteTxLen ){ when( isTLWriteTxLen ){
isTxError := false.B isTxError := false.B
} .elsewhen( isTxFull & isTLWriteTxFifo ){ } .elsewhen( isTxFull & isTLWriteTxFifo ){
isTxError := true.B isTxError := true.B
@@ -122,12 +131,12 @@ trait TLCDRTx{ this: TLCDRBase =>
trait TLCDRRx{ this: TLCDRBase => trait TLCDRRx{ this: TLCDRBase =>
val isTLWriteRxSoftReset = io.tla.fire & io.tla.bits.address(6,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(6,0) === "h14".U & ( io.tla.bits.opcode === 4.U ) // val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(6,0) === "h18".U & ( io.tla.bits.opcode === 4.U ) val isTLReadRxLen = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ) val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
val rxLen = RegInit(0.U(32.W)) val rxLen = RegInit(0.U(12.W))
// val isRxBusy = RegInit(false.B) // val isRxBusy = RegInit(false.B)
val isRxValid = rxFifo.io.enq.fire val isRxValid = rxFifo.io.enq.fire
val isRxError = RegInit(false.B) val isRxError = RegInit(false.B)
@@ -141,49 +150,55 @@ trait TLCDRRx{ this: TLCDRBase =>
val rxCnt = RegInit(0.U(2.W)) val rxCnt = RegInit(0.U(2.W))
val rxData = Reg(UInt(32.W)) val rxData = Reg(UInt(24.W))
when(isTLWriteRxSoftReset ){ when(isTLWriteSoftReset ){
isAxisEnd := false.B isAxisEnd := false.B
} .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){ } .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){
isAxisEnd := true.B isAxisEnd := true.B
} }
when( isTLWriteRxSoftReset ){ when( isTLWriteSoftReset ){
rxCnt := 0.U rxCnt := 0.U
} .elsewhen( CDRIn.io.axis.fire ){ } .elsewhen( CDRIn.io.axis.fire ){
rxCnt := rxCnt + 1.U rxCnt := rxCnt + 1.U
rxData := Mux1H(Seq( rxData := Cat( rxData, CDRIn.io.axis.bits.tdata )
(rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
(rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ), // PriorityMux(Seq(
(rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ), // (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(16.W) /*,0.U(8.W)*/ ),
// (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ), // (rxCnt === 1.U) -> Cat( rxData(23,16), CDRIn.io.axis.bits.tdata, 0.U(8.W) /*,0.U(8.W)*/ ),
)) // (rxCnt === 2.U) -> Cat( rxData(23, 8), CDRIn.io.axis.bits.tdata /*,0.U(8.W)*/ ),
// // (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ),
// ))
} }
when( isTLWriteRxSoftReset ){ when( isTLWriteSoftReset ){
rxLen := 0.U rxLen := 0.U
} .elsewhen( CDRIn.io.axis.fire ){ } .elsewhen( CDRIn.io.axis.fire ){
rxLen := rxLen + 1.U rxLen := rxLen + 1.U
} }
rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.tlast ) rxFifo.io.enq.valid := CDRIn.io.axis.fire & rxCnt === 3.U
rxFifo.io.enq.bits := Mux1H(Seq( rxFifo.io.enq.bits := Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata )
(rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
(rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ), // PriorityMux(Seq(
(rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ), // (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
(rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ), // (rxCnt === 1.U) -> Cat( rxData(23,16), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
)) // (rxCnt === 2.U) -> Cat( rxData(23, 8), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
// (rxCnt === 3.U) -> Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata ),
// ))
assert( ~(( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast) & rxCnt =/= 3.U), "Assert Failed! Rx must 4-byte Align!" )
CDRIn.io.axis.ready := true.B CDRIn.io.axis.ready := true.B
rxFifo.reset := reset.asBool | isTLWriteRxSoftReset rxFifo.reset := reset.asBool | isTLWriteSoftReset
rxFifo.io.deq.ready := isTLReadRxFifo rxFifo.io.deq.ready := isTLReadRxFifo
when( isTLWriteRxSoftReset ){ when( isTLWriteSoftReset ){
isRxError := false.B isRxError := false.B
} .elsewhen( rxFifo.io.enq.valid & ~rxFifo.io.enq.ready ){ } .elsewhen( rxFifo.io.enq.valid & ~rxFifo.io.enq.ready ){
isRxError := true.B isRxError := true.B
@@ -196,21 +211,21 @@ trait TLCDRRx{ this: TLCDRBase =>
class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with TLCDRTx with TLCDRRx{ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with TLCDRTx with TLCDRRx{
val isWriteTransDir = io.tla.fire & io.tla.bits.address(6,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val tlaInfo = Reg(new TLBundleA(edge.bundle)) val tlaInfo = Reg(new TLBundleA(edge.bundle))
val rdata = Reg(UInt(32.W)) val rdata = Reg(UInt(32.W))
val tlAReady = RegInit(true.B) val tlAReady = RegInit(true.B)
val tlDValid = RegInit(false.B) val tlDValid = RegInit(false.B)
val isRead = Reg(Bool()) val isRead = tlaInfo.opcode === 4.U
when( isWriteTransDir ){ when( isWriteTransDir ){
dirSel := io.tla.bits.data dirSel := io.tla.bits.data
} }
io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) ) io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
io.tld.valid := tlDValid io.tld.valid := tlDValid
io.interrupt(0) := intTxError io.interrupt(0) := intTxError
@@ -221,13 +236,6 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
when( io.tla.fire ) { when( io.tla.fire ) {
tlaInfo := io.tla.bits tlaInfo := io.tla.bits
when( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) {
isRead := false.B
} .elsewhen( io.tla.bits.opcode === 4.U ) {
isRead := true.B
} .otherwise{
assert( false.B, "Assert Failed! Unsupport Operation!" )
}
} }
when( io.tla.fire ){ when( io.tla.fire ){
@@ -245,18 +253,8 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
} }
when( isTLReadTxStatus){ when( isTLReadStatus){
rdata := Cat( isTxBusy, isTxFull, isTxError ) rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError )
} .elsewhen(isTLWriteTxLen ){
rdata := 0.U
} .elsewhen(isTLWriteTxFifo ){
rdata := 0.U
} .elsewhen(isTLWriteTxSoftReset){
rdata := 0.U
} .elsewhen(isTLWriteRxSoftReset){
rdata := 0.U
} .elsewhen(isTLReadRxStatus ){
rdata := Cat( isRxValid, isRxError )
} .elsewhen(isTLReadRxLen ){ } .elsewhen(isTLReadRxLen ){
rdata := rxLen rdata := rxLen
} .elsewhen(isTLReadRxFifo ){ } .elsewhen(isTLReadRxFifo ){