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分时复用一个CDR

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This commit is contained in:
RuigeLee
2024-10-31 15:12:32 +08:00
parent 69f3f0e66b
commit 20a52f2506
3 changed files with 38 additions and 46 deletions
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38
src/main/scala/backBoard/pico/BackSystem.scala
View File

@@ -128,13 +128,13 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
val io: BackSysIO = IO(new BackSysIO)
val pico = Module(new Picorv32_tl(edge = core_edge))
val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(cdr_edge)) }
val cdr = Module(new TLCDR(cdr_edge))
val gpio = Module(new SimpleGpio(gpio_edge))
// val trap = Output(Bool())
pico.io.irq := Cat( io.DCIn, cdr(1).io.interrupt.asUInt, cdr(0).io.interrupt.asUInt )
pico.io.irq := Cat( io.DCIn, cdr.io.interrupt.asUInt )
// val eoi = Output(UInt(32.W))
io.out := gpio.io.out
@@ -146,13 +146,12 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
cdr(0).io.overCLK := io.overCLK
cdr(1).io.overCLK := io.overCLK
cdr.io.overCLK := io.overCLK
cdr(0).io.datIn := io.dDatIn
io.dDatOut := cdr(0).io.datOut
cdr(1).io.datIn := io.uDatIn
io.uDatOut := cdr(1).io.datOut
cdr.io.dDatIn := io.dDatIn
io.dDatOut := cdr.io.dDatOut
cdr.io.uDatIn := io.uDatIn
io.uDatOut := cdr.io.uDatOut
io.out := gpio.io.out
@@ -174,25 +173,14 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
cdr(0).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.bits.address(7) === "h0".U
cdr(1).io.tla.valid := cdr_bus.a.valid & cdr_bus.a.bits.address(7) === "h1".U
cdr(0).io.tla.bits := cdr_bus.a.bits
cdr(1).io.tla.bits := cdr_bus.a.bits
cdr_bus.a.ready :=
(cdr_bus.a.bits.address(7) === "h0".U & cdr(0).io.tla.ready) |
(cdr_bus.a.bits.address(7) === "h1".U & cdr(1).io.tla.ready)
cdr_bus.d.valid := cdr(0).io.tld.valid | cdr(1).io.tld.valid
cdr_bus.d.bits := Mux1H(Seq(
cdr(0).io.tld.valid -> cdr(0).io.tld.bits,
cdr(1).io.tld.valid -> cdr(1).io.tld.bits,
))
assert( ~(cdr(0).io.tld.valid & cdr(1).io.tld.valid), "Assert Failed! Two CDR can never resp at the same cycle!" )
cdr(0).io.tld.ready := cdr_bus.d.ready
cdr(1).io.tld.ready := cdr_bus.d.ready
cdr.io.tla.valid := cdr_bus.a.valid & cdr_bus.a.bits.address(7) === "h0".U
cdr.io.tla.bits := cdr_bus.a.bits
cdr_bus.a.ready := cdr.io.tla.ready
cdr_bus.d.valid := cdr.io.tld.valid
cdr_bus.d.bits := cdr.io.tld.bits
cdr.io.tld.ready := cdr_bus.d.ready
gpio.io.tla.valid := gpio_bus.a.valid

23
src/main/scala/backBoard/pico/TLCDR.scala
View File

@@ -11,9 +11,10 @@ import freechips.rocketchip.tilelink._
abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
class TLCDRIO extends Bundle{
val overCLK = Input(Bool())
val datIn = Input(Bool())
val datOut = Output(Bool())
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
@@ -21,14 +22,17 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
val interrupt = Output(Vec(4, Bool()))
}
val io: TLCDRIO = IO(new TLCDRIO)
val io: TLCDRIO = IO(new TLCDRIO)
val dirSel = RegInit(false.B)
val CDRIn = Module(new CDRIn)
CDRIn.io.serDat := io.datIn
CDRIn.io.serDat := Mux( ~dirSel, io.dDatIn, io.uDatIn )
CDRIn.io.overCLK := io.overCLK
val CDROut = Module(new CDROut)
io.datOut := CDROut.io.serDat
io.dDatOut := ~dirSel & CDROut.io.serDat
io.uDatOut := dirSel & CDROut.io.serDat
// CDRIn.io.axis = Decoupled(new AXIS_Bundle(8))
@@ -192,6 +196,8 @@ trait TLCDRRx{ this: TLCDRBase =>
class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with TLCDRTx with TLCDRRx{
val isWriteTransDir = io.tla.fire & io.tla.bits.address(6,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val tlaInfo = Reg(new TLBundleA(edge.bundle))
val rdata = Reg(UInt(32.W))
val tlAReady = RegInit(true.B)
@@ -199,6 +205,11 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
val isRead = Reg(Bool())
when( isWriteTransDir ){
dirSel := io.tla.bits.data
}
io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
io.tld.valid := tlDValid

23
tb/sw/src/SlvMain.c
View File

@@ -4,23 +4,16 @@
// #include "gpio.h"
// #include "timer.h"
volatile uint32_t *cdr_0_tx_status = (uint32_t*)( 0x40000000 + 0x0 ); //read
volatile uint32_t *cdr_0_tx_txLen = (uint32_t*)( 0x40000000 + 0x4 ); //write
volatile uint32_t *cdr_0_tx_txFifo = (uint32_t*)( 0x40000000 + 0x8 ); //write
volatile uint32_t *cdr_tx_status = (uint32_t*)( 0x40000000 + 0x0 ); //read
volatile uint32_t *cdr_tx_txLen = (uint32_t*)( 0x40000000 + 0x4 ); //write
volatile uint32_t *cdr_tx_txFifo = (uint32_t*)( 0x40000000 + 0x8 ); //write
volatile uint32_t *cdr_TransDir = (uint32_t*)( 0x40000000 + 0xc ); //write
volatile uint32_t *cdr_0_rx_softReset = (uint32_t*)( 0x40000000 + 0x10 ); //write
volatile uint32_t *cdr_0_rx_status = (uint32_t*)( 0x40000000 + 0x14 ); //read
volatile uint32_t *cdr_0_rx_rxLen = (uint32_t*)( 0x40000000 + 0x18 ); //read
volatile uint32_t *cdr_0_rx_rxFifo = (uint32_t*)( 0x40000000 + 0x1c ); //read
volatile uint32_t *cdr_rx_softReset = (uint32_t*)( 0x40000000 + 0x10 ); //write
volatile uint32_t *cdr_rx_status = (uint32_t*)( 0x40000000 + 0x14 ); //read
volatile uint32_t *cdr_rx_rxLen = (uint32_t*)( 0x40000000 + 0x18 ); //read
volatile uint32_t *cdr_rx_rxFifo = (uint32_t*)( 0x40000000 + 0x1c ); //read
volatile uint32_t *cdr_1_tx_status = (uint32_t*)( 0x40000080 + 0x0 ); //read
volatile uint32_t *cdr_1_tx_txLen = (uint32_t*)( 0x40000080 + 0x4 ); //write
volatile uint32_t *cdr_1_tx_txFifo = (uint32_t*)( 0x40000080 + 0x8 ); //write
volatile uint32_t *cdr_1_rx_softReset = (uint32_t*)( 0x40000080 + 0x10 ); //write
volatile uint32_t *cdr_1_rx_status = (uint32_t*)( 0x40000080 + 0x14 ); //read
volatile uint32_t *cdr_1_rx_rxLen = (uint32_t*)( 0x40000080 + 0x18 ); //read
volatile uint32_t *cdr_1_rx_rxFifo = (uint32_t*)( 0x40000080 + 0x1c ); //read
volatile uint32_t *WriteGpio = (uint32_t*) ( 0x60000000);
volatile uint32_t *ReadGpio = (uint32_t*) ( 0x60000000);