From 46882b6b4dc092b25f5614c2d5115815ce4c379e Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 31 Oct 2024 17:38:12 +0800 Subject: [PATCH] =?UTF-8?q?=E7=BC=A9=E5=87=8F=E5=90=8E=E9=9D=A2=E7=A7=AF?= =?UTF-8?q?=E5=B7=B2=E7=BB=8F=E6=BB=A1=E8=B6=B3=E8=A6=81=E6=B1=82=EF=BC=8C?= =?UTF-8?q?=E6=97=B6=E5=BA=8F=E8=BF=9D=E4=BE=8B=EF=BC=8C=E4=B8=BB=E8=A6=81?= =?UTF-8?q?=E9=9B=86=E4=B8=AD=E5=9C=A8alu=E5=92=8C=E8=AE=BF=E5=AD=98?= =?UTF-8?q?=E6=8E=A5=E5=8F=A3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 28 ++-- src/main/scala/backBoard/ebus/CDROut.scala | 6 +- .../scala/backBoard/pico/BackSystem.scala | 4 +- src/main/scala/backBoard/pico/TLCDR.scala | 120 +++++++++--------- 4 files changed, 77 insertions(+), 81 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index a52d026..5671b5b 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -57,7 +57,7 @@ trait CDRInOverSample{ this: CDRInBase => // (sampleReg(2) & sampleReg(1) & sampleReg(0)) val syncSerDat = ShiftRegister( - Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } ) + PriorityMux( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } ) , 2 ) } @@ -66,8 +66,8 @@ trait CDRInAxis{ this: CDRInBase => def HeaderByte: Int = 8 - val ETH_PRE = "h55".U - val ETH_SFD = "hD5".U + val ETH_PRE = "h55".U(8.W) + val ETH_SFD = "hD5".U(8.W) val STATE_IDLE = 0.U val STATE_HEADER = 1.U @@ -85,22 +85,20 @@ trait CDRInAxis{ this: CDRInBase => val crcCmp = Reg(UInt(32.W)) val bitCnt = Reg(UInt(3.W)) - val byteCnt = RegInit(0.U(16.W)) + val byteCnt = RegInit(0.U(12.W)) val syncSerDat: Bool - val shiftData = RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat) + val checkSFD = RegInit( 0.U(16.W) ); checkSFD := Cat( checkSFD(14,0), syncSerDat ) - val header = Reg(UInt((8*HeaderByte).W)) - val payloadLen = header(63,52) - val operation = header(51,48) - val param = header(47, 0) + val shiftData = checkSFD(7,0) //RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat) + + val payloadLen = RegEnable( shiftData, byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER ) val isArbLock: Bool - val checkSFD = ShiftRegister( shiftData, 8 ) stateNext := Mux1H(Seq( - (stateCurr === STATE_IDLE) -> ( Mux( isArbLock & checkSFD === ETH_PRE & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE + (stateCurr === STATE_IDLE) -> ( Mux( isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ), (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD (stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC @@ -110,13 +108,13 @@ trait CDRInAxis{ this: CDRInBase => - when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock & checkSFD === ETH_PRE ){ //first align + when( stateCurr === STATE_IDLE & isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD) ){ //first align bitCnt := 0.U } .otherwise{ bitCnt := bitCnt + 1.U } - when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock & checkSFD === ETH_PRE ){ //first align + when( stateCurr === STATE_IDLE & isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD) ){ //first align byteCnt := 0.U } .elsewhen( bitCnt === 7.U ){ when( stateCurr === STATE_HEADER ){ @@ -131,9 +129,7 @@ trait CDRInAxis{ this: CDRInBase => } } - when( stateCurr === STATE_HEADER & bitCnt === 7.U ){ - header := Cat( header( 8*HeaderByte-1-8, 0), shiftData ) - } + diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala index aac3cc0..553004e 100644 --- a/src/main/scala/backBoard/ebus/CDROut.scala +++ b/src/main/scala/backBoard/ebus/CDROut.scala @@ -36,7 +36,7 @@ class CDROut extends Module{ val bitCnt = Reg(UInt(3.W)) - val byteCnt = Reg(UInt(16.W)) + val byteCnt = Reg(UInt(3.W)) //payload dont need to count val crcOut = crcUnit.io.crc val reset_crc = stateCurr === STATE_IDLE @@ -77,7 +77,7 @@ class CDROut extends Module{ } .elsewhen( stateCurr === STATE_PAYLOAD ){ shiftData := io.axis.bits.tdata } .elsewhen( stateCurr === STATE_FCS ){ - shiftData := Mux1H(Seq( + shiftData := PriorityMux(Seq( ( byteCnt === 0.U) -> ~crcOut( 7,0), ( byteCnt === 1.U) -> ~crcOut(15,8), ( byteCnt === 2.U) -> ~crcOut(23,16), @@ -94,7 +94,7 @@ class CDROut extends Module{ bitCnt := bitCnt + 1.U } - when( stateNext =/= stateCurr ){ + when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){ byteCnt := 0.U } .elsewhen( bitCnt === 7.U ){ byteCnt := byteCnt + 1.U diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala index e1a717c..6503872 100644 --- a/src/main/scala/backBoard/pico/BackSystem.scala +++ b/src/main/scala/backBoard/pico/BackSystem.scala @@ -92,7 +92,9 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter )), beatBytes = 32/8))) - val xbar = TLXbar() + val xbar = TLXbar( + //policy = TLArbiter.lowestIndexFirst + ) xbar := coreClientNode cdrNode := xbar sram.node := xbar diff --git a/src/main/scala/backBoard/pico/TLCDR.scala b/src/main/scala/backBoard/pico/TLCDR.scala index f71b272..817948f 100644 --- a/src/main/scala/backBoard/pico/TLCDR.scala +++ b/src/main/scala/backBoard/pico/TLCDR.scala @@ -39,21 +39,20 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac // CDROut.io.axis = Flipped(Decoupled(new AXIS_Bundle(8))) - val txFifo = Module(new Queue(UInt(32.W), 8)) - val rxFifo = Module(new Queue(UInt(32.W), 8)) + val txFifo = Module(new Queue(UInt(32.W), 4)) + val rxFifo = Module(new Queue(UInt(32.W), 4)) } trait TLCDRTx{ this: TLCDRBase => - val isTLReadTxStatus = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( io.tla.bits.opcode === 4.U ) - val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(6,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - val isTLWriteTxSoftReset = isTLWriteTxLen + val isTLReadStatus = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U ) + val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - val txLen = RegInit(0.U(32.W)) + val txLen = RegInit(0.U(12.W)) val isTxBusy = RegInit(false.B) val isTxFull = ~txFifo.io.enq.ready val isTxError = RegInit(false.B) @@ -64,18 +63,28 @@ trait TLCDRTx{ this: TLCDRBase => val txCnt = Reg(UInt(2.W)) - val txData = RegEnable( txFifo.io.deq.bits, txFifo.io.deq.fire) + val txData = Reg(UInt(32.W)) + + when( txFifo.io.deq.fire ){ //txCnt === 3.U + txData := txFifo.io.deq.bits + assert(CDROut.io.axis.fire) + } .elsewhen( CDROut.io.axis.fire ){ + txData := txData << 8 + } + txFifo.io.deq.ready := Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B ) txFifo.reset := reset.asBool | isTLWriteTxLen - CDROut.io.axis.bits.tdata := Mux1H(Seq( - (txCnt === 0.U) -> txData(31, 24), - (txCnt === 1.U) -> txData(23, 16), - (txCnt === 2.U) -> txData(15, 8), - (txCnt === 3.U) -> txData( 7, 0), - )) + CDROut.io.axis.bits.tdata := txData.head(8) + + // PriorityMux(Seq( + // (txCnt === 0.U) -> txData(31, 24), + // (txCnt === 1.U) -> txData(23, 16), + // (txCnt === 2.U) -> txData(15, 8), + // (txCnt === 3.U) -> txData( 7, 0), + // )) CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U CDROut.io.axis.bits.tuser := isTxError @@ -107,7 +116,7 @@ trait TLCDRTx{ this: TLCDRBase => txFifo.io.enq.bits := io.tla.bits.data txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U - when( isTLReadTxStatus | isTLWriteTxLen ){ + when( isTLWriteTxLen ){ isTxError := false.B } .elsewhen( isTxFull & isTLWriteTxFifo ){ isTxError := true.B @@ -122,12 +131,12 @@ trait TLCDRTx{ this: TLCDRBase => trait TLCDRRx{ this: TLCDRBase => - val isTLWriteRxSoftReset = io.tla.fire & io.tla.bits.address(6,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) - val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(6,0) === "h14".U & ( io.tla.bits.opcode === 4.U ) - val isTLReadRxLen = io.tla.fire & io.tla.bits.address(6,0) === "h18".U & ( io.tla.bits.opcode === 4.U ) - val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ) + val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + // val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U ) + val isTLReadRxLen = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U ) + val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ) - val rxLen = RegInit(0.U(32.W)) + val rxLen = RegInit(0.U(12.W)) // val isRxBusy = RegInit(false.B) val isRxValid = rxFifo.io.enq.fire val isRxError = RegInit(false.B) @@ -141,49 +150,55 @@ trait TLCDRRx{ this: TLCDRBase => val rxCnt = RegInit(0.U(2.W)) - val rxData = Reg(UInt(32.W)) + val rxData = Reg(UInt(24.W)) - when(isTLWriteRxSoftReset ){ + when(isTLWriteSoftReset ){ isAxisEnd := false.B } .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){ isAxisEnd := true.B } - when( isTLWriteRxSoftReset ){ + when( isTLWriteSoftReset ){ rxCnt := 0.U } .elsewhen( CDRIn.io.axis.fire ){ rxCnt := rxCnt + 1.U - rxData := Mux1H(Seq( - (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ), - (rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ), - (rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ), - // (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ), - )) + rxData := Cat( rxData, CDRIn.io.axis.bits.tdata ) + + // PriorityMux(Seq( + // (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(16.W) /*,0.U(8.W)*/ ), + // (rxCnt === 1.U) -> Cat( rxData(23,16), CDRIn.io.axis.bits.tdata, 0.U(8.W) /*,0.U(8.W)*/ ), + // (rxCnt === 2.U) -> Cat( rxData(23, 8), CDRIn.io.axis.bits.tdata /*,0.U(8.W)*/ ), + // // (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ), + // )) } - when( isTLWriteRxSoftReset ){ + when( isTLWriteSoftReset ){ rxLen := 0.U } .elsewhen( CDRIn.io.axis.fire ){ rxLen := rxLen + 1.U } - rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.tlast ) - rxFifo.io.enq.bits := Mux1H(Seq( - (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ), - (rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ), - (rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ), - (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ), - )) + rxFifo.io.enq.valid := CDRIn.io.axis.fire & rxCnt === 3.U + rxFifo.io.enq.bits := Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata ) + + // PriorityMux(Seq( + // (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ), + // (rxCnt === 1.U) -> Cat( rxData(23,16), CDRIn.io.axis.bits.tdata, 0.U(16.W) ), + // (rxCnt === 2.U) -> Cat( rxData(23, 8), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ), + // (rxCnt === 3.U) -> Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata ), + // )) + assert( ~(( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast) & rxCnt =/= 3.U), "Assert Failed! Rx must 4-byte Align!" ) + CDRIn.io.axis.ready := true.B - rxFifo.reset := reset.asBool | isTLWriteRxSoftReset + rxFifo.reset := reset.asBool | isTLWriteSoftReset rxFifo.io.deq.ready := isTLReadRxFifo - when( isTLWriteRxSoftReset ){ + when( isTLWriteSoftReset ){ isRxError := false.B } .elsewhen( rxFifo.io.enq.valid & ~rxFifo.io.enq.ready ){ isRxError := true.B @@ -196,21 +211,21 @@ trait TLCDRRx{ this: TLCDRBase => class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with TLCDRTx with TLCDRRx{ - val isWriteTransDir = io.tla.fire & io.tla.bits.address(6,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) val tlaInfo = Reg(new TLBundleA(edge.bundle)) val rdata = Reg(UInt(32.W)) val tlAReady = RegInit(true.B) val tlDValid = RegInit(false.B) - val isRead = Reg(Bool()) + val isRead = tlaInfo.opcode === 4.U when( isWriteTransDir ){ dirSel := io.tla.bits.data } - io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) ) + io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) ) io.tld.valid := tlDValid io.interrupt(0) := intTxError @@ -221,13 +236,6 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with when( io.tla.fire ) { tlaInfo := io.tla.bits - when( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) { - isRead := false.B - } .elsewhen( io.tla.bits.opcode === 4.U ) { - isRead := true.B - } .otherwise{ - assert( false.B, "Assert Failed! Unsupport Operation!" ) - } } when( io.tla.fire ){ @@ -245,18 +253,8 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with } - when( isTLReadTxStatus){ - rdata := Cat( isTxBusy, isTxFull, isTxError ) - } .elsewhen(isTLWriteTxLen ){ - rdata := 0.U - } .elsewhen(isTLWriteTxFifo ){ - rdata := 0.U - } .elsewhen(isTLWriteTxSoftReset){ - rdata := 0.U - } .elsewhen(isTLWriteRxSoftReset){ - rdata := 0.U - } .elsewhen(isTLReadRxStatus ){ - rdata := Cat( isRxValid, isRxError ) + when( isTLReadStatus){ + rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError ) } .elsewhen(isTLReadRxLen ){ rdata := rxLen } .elsewhen(isTLReadRxFifo ){