缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口

src/main/scala/backBoard/pico/TLCDR.scala

@@ -39,21 +39,20 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
   // CDROut.io.axis = Flipped(Decoupled(new AXIS_Bundle(8))) 
 
 
-  val txFifo = Module(new Queue(UInt(32.W), 8))
-  val rxFifo = Module(new Queue(UInt(32.W), 8))
+  val txFifo = Module(new Queue(UInt(32.W), 4))
+  val rxFifo = Module(new Queue(UInt(32.W), 4))
 
 }
 
 
 trait TLCDRTx{ this: TLCDRBase =>
 
-  val isTLReadTxStatus      = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
-  val isTLWriteTxLen        = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
-  val isTLWriteTxFifo       = io.tla.fire & io.tla.bits.address(6,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
-  val isTLWriteTxSoftReset  = isTLWriteTxLen
+  val isTLReadStatus        = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
+  val isTLWriteTxLen        = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
+  val isTLWriteTxFifo       = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
 
 
-  val txLen     = RegInit(0.U(32.W))
+  val txLen     = RegInit(0.U(12.W))
   val isTxBusy  = RegInit(false.B)
   val isTxFull  = ~txFifo.io.enq.ready
   val isTxError = RegInit(false.B)
@@ -64,18 +63,28 @@ trait TLCDRTx{ this: TLCDRBase =>
 
   val txCnt = Reg(UInt(2.W))
 
-  val txData = RegEnable( txFifo.io.deq.bits, txFifo.io.deq.fire)
+  val txData = Reg(UInt(32.W))
+
+  when( txFifo.io.deq.fire ){ //txCnt === 3.U
+    txData := txFifo.io.deq.bits
+    assert(CDROut.io.axis.fire)
+  } .elsewhen( CDROut.io.axis.fire ){
+    txData := txData << 8
+  }
+  
   txFifo.io.deq.ready := 
     Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B )
 
   txFifo.reset := reset.asBool | isTLWriteTxLen
 
-  CDROut.io.axis.bits.tdata := Mux1H(Seq(
-    (txCnt === 0.U) -> txData(31, 24),
-    (txCnt === 1.U) -> txData(23, 16),
-    (txCnt === 2.U) -> txData(15,  8),
-    (txCnt === 3.U) -> txData( 7,  0),
-  ))
+  CDROut.io.axis.bits.tdata := txData.head(8)
+
+  // PriorityMux(Seq(
+  //   (txCnt === 0.U) -> txData(31, 24),
+  //   (txCnt === 1.U) -> txData(23, 16),
+  //   (txCnt === 2.U) -> txData(15,  8),
+  //   (txCnt === 3.U) -> txData( 7,  0),
+  // ))
 
   CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U
   CDROut.io.axis.bits.tuser := isTxError
@@ -107,7 +116,7 @@ trait TLCDRTx{ this: TLCDRBase =>
   txFifo.io.enq.bits  := io.tla.bits.data
   txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U
 
-  when( isTLReadTxStatus | isTLWriteTxLen ){
+  when( isTLWriteTxLen ){
     isTxError := false.B
   } .elsewhen( isTxFull & isTLWriteTxFifo ){
     isTxError := true.B
@@ -122,12 +131,12 @@ trait TLCDRTx{ this: TLCDRBase =>
 
 trait TLCDRRx{ this: TLCDRBase => 
 
-  val isTLWriteRxSoftReset = io.tla.fire & io.tla.bits.address(6,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
-  val isTLReadRxStatus     = io.tla.fire & io.tla.bits.address(6,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
-  val isTLReadRxLen        = io.tla.fire & io.tla.bits.address(6,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
-  val isTLReadRxFifo       = io.tla.fire & io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
+  val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
+  // val isTLReadRxStatus     = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
+  val isTLReadRxLen        = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
+  val isTLReadRxFifo       = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
 
-  val rxLen     = RegInit(0.U(32.W))
+  val rxLen     = RegInit(0.U(12.W))
   // val isRxBusy  = RegInit(false.B)
   val isRxValid = rxFifo.io.enq.fire
   val isRxError = RegInit(false.B)
@@ -141,49 +150,55 @@ trait TLCDRRx{ this: TLCDRBase =>
 
 
   val rxCnt = RegInit(0.U(2.W))
-  val rxData = Reg(UInt(32.W))
+  val rxData = Reg(UInt(24.W))
 
-  when(isTLWriteRxSoftReset ){
+  when(isTLWriteSoftReset ){
     isAxisEnd := false.B
   } .elsewhen( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast ){
     isAxisEnd := true.B
   }
 
   
-  when( isTLWriteRxSoftReset ){
+  when( isTLWriteSoftReset ){
     rxCnt := 0.U
   } .elsewhen( CDRIn.io.axis.fire ){
     rxCnt :=  rxCnt + 1.U
 
-    rxData := Mux1H(Seq(
-      (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
-      (rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
-      (rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
-      // (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata  ),
-    ))
+    rxData := Cat( rxData, CDRIn.io.axis.bits.tdata )
+
+    // PriorityMux(Seq(
+    //   (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(16.W) /*,0.U(8.W)*/ ), 
+    //   (rxCnt === 1.U) -> Cat( rxData(23,16), CDRIn.io.axis.bits.tdata, 0.U(8.W) /*,0.U(8.W)*/ ),
+    //   (rxCnt === 2.U) -> Cat( rxData(23, 8), CDRIn.io.axis.bits.tdata /*,0.U(8.W)*/         ),
+    //   // (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata  ),
+    // ))
   }
 
-  when( isTLWriteRxSoftReset ){
+  when( isTLWriteSoftReset ){
     rxLen := 0.U
   } .elsewhen( CDRIn.io.axis.fire ){
     rxLen := rxLen + 1.U
   }
 
-  rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.tlast )
-  rxFifo.io.enq.bits  := Mux1H(Seq(
-      (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
-      (rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
-      (rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
-      (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata  ),
-    ))
+  rxFifo.io.enq.valid := CDRIn.io.axis.fire & rxCnt === 3.U
+  rxFifo.io.enq.bits  := Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata  )
+  
+  // PriorityMux(Seq(
+  //     (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
+  //     (rxCnt === 1.U) -> Cat( rxData(23,16), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
+  //     (rxCnt === 2.U) -> Cat( rxData(23, 8), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
+  //     (rxCnt === 3.U) -> Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata  ),
+  //   ))
+  assert( ~(( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast) & rxCnt =/= 3.U), "Assert Failed! Rx must 4-byte Align!" )
+
   CDRIn.io.axis.ready := true.B
 
-  rxFifo.reset := reset.asBool | isTLWriteRxSoftReset
+  rxFifo.reset := reset.asBool | isTLWriteSoftReset
 
   rxFifo.io.deq.ready := isTLReadRxFifo
 
 
-  when( isTLWriteRxSoftReset ){
+  when( isTLWriteSoftReset ){
     isRxError := false.B
   } .elsewhen( rxFifo.io.enq.valid & ~rxFifo.io.enq.ready ){
     isRxError := true.B
@@ -196,21 +211,21 @@ trait TLCDRRx{ this: TLCDRBase =>
 
 class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with TLCDRTx with TLCDRRx{
 
-  val isWriteTransDir       = io.tla.fire & io.tla.bits.address(6,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
+  val isWriteTransDir       = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
 
   val tlaInfo = Reg(new TLBundleA(edge.bundle))
   val rdata = Reg(UInt(32.W))
   val tlAReady  = RegInit(true.B)
   val tlDValid = RegInit(false.B)
 
-  val isRead  = Reg(Bool())
+  val isRead = tlaInfo.opcode === 4.U
 
   when( isWriteTransDir ){
     dirSel := io.tla.bits.data
   }
 
 
-  io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(6,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
+  io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
   io.tld.valid := tlDValid 
 
   io.interrupt(0) := intTxError
@@ -221,13 +236,6 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
 
   when( io.tla.fire ) {
     tlaInfo := io.tla.bits
-    when( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) {
-      isRead := false.B
-    } .elsewhen( io.tla.bits.opcode === 4.U ) {
-      isRead := true.B
-    } .otherwise{
-      assert( false.B, "Assert Failed! Unsupport Operation!" )
-    }
   }
 
   when( io.tla.fire ){
@@ -245,18 +253,8 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
   }
   
 
-  when( isTLReadTxStatus){
-    rdata := Cat( isTxBusy, isTxFull, isTxError )
-  } .elsewhen(isTLWriteTxLen      ){
-    rdata := 0.U
-  } .elsewhen(isTLWriteTxFifo     ){
-    rdata := 0.U
-  } .elsewhen(isTLWriteTxSoftReset){
-    rdata := 0.U
-  } .elsewhen(isTLWriteRxSoftReset){
-    rdata := 0.U
-  } .elsewhen(isTLReadRxStatus    ){
-    rdata := Cat( isRxValid, isRxError )
+  when( isTLReadStatus){
+    rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError )
   } .elsewhen(isTLReadRxLen       ){
     rdata := rxLen
   } .elsewhen(isTLReadRxFifo      ){