缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口

src/main/scala/backBoard/ebus/CDROut.scala

@@ -36,7 +36,7 @@ class CDROut extends Module{
 
 
   val bitCnt = Reg(UInt(3.W))
-  val byteCnt = Reg(UInt(16.W))
+  val byteCnt = Reg(UInt(3.W)) //payload dont need to count
 
   val crcOut = crcUnit.io.crc
   val reset_crc = stateCurr === STATE_IDLE 
@@ -77,7 +77,7 @@ class CDROut extends Module{
       } .elsewhen( stateCurr === STATE_PAYLOAD ){
         shiftData := io.axis.bits.tdata
       } .elsewhen( stateCurr === STATE_FCS ){
-        shiftData := Mux1H(Seq(
+        shiftData := PriorityMux(Seq(
           ( byteCnt === 0.U) -> ~crcOut( 7,0),
           ( byteCnt === 1.U) -> ~crcOut(15,8),
           ( byteCnt === 2.U) -> ~crcOut(23,16),
@@ -94,7 +94,7 @@ class CDROut extends Module{
     bitCnt := bitCnt + 1.U
   }
 
-  when( stateNext =/= stateCurr ){
+  when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
     byteCnt := 0.U
   } .elsewhen( bitCnt === 7.U ){
     byteCnt := byteCnt + 1.U