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缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口

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This commit is contained in:
RuigeLee
2024-10-31 17:38:12 +08:00
parent 20a52f2506
commit 46882b6b4d
4 changed files with 77 additions and 81 deletions
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28
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -57,7 +57,7 @@ trait CDRInOverSample{ this: CDRInBase =>
// (sampleReg(2) & sampleReg(1) & sampleReg(0))
val syncSerDat = ShiftRegister(
Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
PriorityMux( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
, 2 )
}
@@ -66,8 +66,8 @@ trait CDRInAxis{ this: CDRInBase =>
def HeaderByte: Int = 8
val ETH_PRE = "h55".U
val ETH_SFD = "hD5".U
val ETH_PRE = "h55".U(8.W)
val ETH_SFD = "hD5".U(8.W)
val STATE_IDLE = 0.U
val STATE_HEADER = 1.U
@@ -85,22 +85,20 @@ trait CDRInAxis{ this: CDRInBase =>
val crcCmp = Reg(UInt(32.W))
val bitCnt = Reg(UInt(3.W))
val byteCnt = RegInit(0.U(16.W))
val byteCnt = RegInit(0.U(12.W))
val syncSerDat: Bool
val shiftData = RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat)
val checkSFD = RegInit( 0.U(16.W) ); checkSFD := Cat( checkSFD(14,0), syncSerDat )
val header = Reg(UInt((8*HeaderByte).W))
val payloadLen = header(63,52)
val operation = header(51,48)
val param = header(47, 0)
val shiftData = checkSFD(7,0) //RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat)
val payloadLen = RegEnable( shiftData, byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER )
val isArbLock: Bool
val checkSFD = ShiftRegister( shiftData, 8 )
stateNext :=
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( isArbLock & checkSFD === ETH_PRE & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_IDLE) -> ( Mux( isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD
(stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
@@ -110,13 +108,13 @@ trait CDRInAxis{ this: CDRInBase =>
when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock & checkSFD === ETH_PRE ){ //first align
when( stateCurr === STATE_IDLE & isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD) ){ //first align
bitCnt := 0.U
} .otherwise{
bitCnt := bitCnt + 1.U
}
when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock & checkSFD === ETH_PRE ){ //first align
when( stateCurr === STATE_IDLE & isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD) ){ //first align
byteCnt := 0.U
} .elsewhen( bitCnt === 7.U ){
when( stateCurr === STATE_HEADER ){
@@ -131,9 +129,7 @@ trait CDRInAxis{ this: CDRInBase =>
}
}
when( stateCurr === STATE_HEADER & bitCnt === 7.U ){
header := Cat( header( 8*HeaderByte-1-8, 0), shiftData )
}

6
src/main/scala/backBoard/ebus/CDROut.scala
View File

@@ -36,7 +36,7 @@ class CDROut extends Module{
val bitCnt = Reg(UInt(3.W))
val byteCnt = Reg(UInt(16.W))
val byteCnt = Reg(UInt(3.W)) //payload dont need to count
val crcOut = crcUnit.io.crc
val reset_crc = stateCurr === STATE_IDLE
@@ -77,7 +77,7 @@ class CDROut extends Module{
} .elsewhen( stateCurr === STATE_PAYLOAD ){
shiftData := io.axis.bits.tdata
} .elsewhen( stateCurr === STATE_FCS ){
shiftData := Mux1H(Seq(
shiftData := PriorityMux(Seq(
( byteCnt === 0.U) -> ~crcOut( 7,0),
( byteCnt === 1.U) -> ~crcOut(15,8),
( byteCnt === 2.U) -> ~crcOut(23,16),
@@ -94,7 +94,7 @@ class CDROut extends Module{
bitCnt := bitCnt + 1.U
}
when( stateNext =/= stateCurr ){
when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
byteCnt := 0.U
} .elsewhen( bitCnt === 7.U ){
byteCnt := byteCnt + 1.U