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we use async reset for different clock now

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This commit is contained in:
RuigeLee
2023-07-24 19:31:20 +08:00
parent 21f8547273
commit 440cefb02a
2 changed files with 2 additions and 37 deletions
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4
src/main/scala/mac/MacTilelink.scala
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@@ -1140,7 +1140,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
trait MacTileLinkTXClk{ this: MacTileLinkBase => trait MacTileLinkTXClk{ this: MacTileLinkBase =>
withClockAndReset( io.MTxClk.asClock, reset ) { withClockAndReset( io.MTxClk.asClock, reset.asAsyncReset ) {
val Flop = RegInit(false.B) val Flop = RegInit(false.B)
// Synchronizing BlockingTxStatusWrite to MTxClk // Synchronizing BlockingTxStatusWrite to MTxClk
@@ -1313,7 +1313,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
trait MacTileLinkRXClk{ this: MacTileLinkBase => trait MacTileLinkRXClk{ this: MacTileLinkBase =>
withClockAndReset( io.MRxClk.asClock, reset ){ withClockAndReset( io.MRxClk.asClock, reset.asAsyncReset ){
val RxDataLatched2 = RegInit(0.U(32.W)); RxDataLatched2_rxclk := RxDataLatched2 val RxDataLatched2 = RegInit(0.U(32.W)); RxDataLatched2_rxclk := RxDataLatched2
val RxDataLatched1 = RegInit(0.U(24.W)) // Big Endian Byte Ordering[31:8] val RxDataLatched1 = RegInit(0.U(24.W)) // Big Endian Byte Ordering[31:8]

35
src/main/scala/mac/Rocket/RocketMac.scala
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@@ -1,35 +0,0 @@
// package Top
// import chisel3._
// import Mac._
// import freechips.rocketchip.system._
// import org.chipsalliance.cde.config.Parameters
// import freechips.rocketchip.subsystem._
// import freechips.rocketchip.devices.tilelink._
// import freechips.rocketchip.util.DontTouch
// /** Example Top with periphery devices and ports, and a Rocket subsystem */
// class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem
// with HasAsyncExtInterrupts
// with CanHaveMasterAXI4MemPort
// with CanHaveMasterAXI4MMIOPort
// with CanHaveSlaveAXI4Port
// with WithManyMacMix
// {
// // optionally add ROM devices
// // Note that setting BootROMLocated will override the reset_vector for all tiles
// val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
// val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
// override lazy val module = new ExampleRocketSystemModuleImp(this)
// }
// class ExampleRocketSystemModuleImp[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModuleImp(_outer)
// with HasRTCModuleImp
// with HasExtInterruptsModuleImp
// with DontTouch