1479 lines
41 KiB
Scala
1479 lines
41 KiB
Scala
package MAC
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.diplomacy._
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import org.chipsalliance.cde.config._
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abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Module{
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class MacTileLinkSlaveIO extends Bundle{
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val A = Flipped(Decoupled(new TLBundleA(edgeIn.bundle)))
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val D = Decoupled(new TLBundleD(edgeIn.bundle))
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}
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class MacTileLinkMasterIO extends Bundle{
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val A = Decoupled(new TLBundleA(edgeOut.bundle))
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val D = Flipped(Decoupled(new TLBundleD(edgeOut.bundle)))
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}
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class MacTileLinkIO extends Bundle{
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val tlSlv = new MacTileLinkSlaveIO
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val tlMst = new MacTileLinkMasterIO
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// Rx Status signals
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val InvalidSymbol = Input(Bool()) // Invalid symbol was received during reception in 100 Mbps mode
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val LatchedCrcError = Input(Bool()) // CRC error
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val RxLateCollision = Input(Bool()) // Late collision occured while receiving frame
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val ShortFrame = Input(Bool()) // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
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val DribbleNibble = Input(Bool()) // Extra nibble received
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val ReceivedPacketTooBig = Input(Bool()) // Received packet is bigger than r_MaxFL
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val RxLength = Input(UInt(16.W)) // Length of the incoming frame
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val LoadRxStatus = Input(Bool()) // Rx status was loaded
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val ReceivedPacketGood = Input(Bool()) // Received packet's length and CRC are good
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val AddressMiss = Input(Bool()) // When a packet is received AddressMiss status is written to the Rx BD
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val r_RxFlow = Input(Bool())
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val r_PassAll = Input(Bool())
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val ReceivedPauseFrm = Input(Bool())
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// Tx Status signals
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val RetryCntLatched = Input(UInt(4.W)) // Latched Retry Counter
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val RetryLimit = Input(Bool()) // Retry limit reached (Retry Max value +1 attempts were made)
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val LateCollLatched = Input(Bool()) // Late collision occured
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val DeferLatched = Input(Bool()) // Defer indication (Frame was defered before sucessfully sent)
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val RstDeferLatched = Output(Bool())
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val CarrierSenseLost = Input(Bool()) // Carrier Sense was lost during the frame transmission
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// Tx
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val MTxClk = Input(Bool()) // Transmit clock (from PHY)
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val TxUsedData = Input(Bool()) // Transmit packet used data
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val TxRetry = Input(Bool()) // Transmit packet retry
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val TxAbort = Input(Bool()) // Transmit packet abort
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val TxDone = Input(Bool()) // Transmission ended
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val TxStartFrm = Output(Bool()) // Transmit packet start frame
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val TxEndFrm = Output(Bool()) // Transmit packet end frame
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val TxData = Output(UInt(8.W)) // Transmit packet data byte
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val TxUnderRun = Output(Bool()) // Transmit packet under-run
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val PerPacketCrcEn = Output(Bool()) // Per packet crc enable
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val PerPacketPad = Output(Bool()) // Per packet pading
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// Rx
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val MRxClk = Input(Bool()) // Receive clock (from PHY)
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val RxData = Input(UInt(8.W)) // Received data byte (from PHY)
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val RxValid = Input(Bool())
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val RxStartFrm = Input(Bool())
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val RxEndFrm = Input(Bool())
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val RxAbort = Input(Bool()) // This signal is set when address doesn't match.
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val RxStatusWriteLatched_sync2 = Output(Bool())
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//Register
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val r_TxEn = Input(Bool()) // Transmit enable
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val r_RxEn = Input(Bool()) // Receive enable
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val r_TxBDNum = Input(UInt(8.W)) // Receive buffer descriptor number
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// Interrupts
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val TxB_IRQ = Output(Bool())
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val TxE_IRQ = Output(Bool())
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val RxB_IRQ = Output(Bool())
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val RxE_IRQ = Output(Bool())
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val Busy_IRQ = Output(Bool())
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}
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val io = IO(new MacTileLinkIO)
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val (_, _, isLastD, transDCnt) = edgeOut.count(io.tlMst.D)
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val BDCs = Wire(UInt(4.W))
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val TxB_IRQ = RegInit(false.B); io.TxB_IRQ := TxB_IRQ
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val TxE_IRQ = RegInit(false.B); io.TxE_IRQ := TxE_IRQ
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val RxB_IRQ = RegInit(false.B); io.RxB_IRQ := RxB_IRQ
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val RxE_IRQ = RegInit(false.B); io.RxE_IRQ := RxE_IRQ
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val TxUnderRun_wb = RegInit(false.B)
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val TxBDRead = RegInit(true.B)
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val TxStatusWrite = Wire(Bool())
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val TxLength = RegInit(0.U(16.W))
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val LatchedTxLength = RegInit(0.U(16.W))
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val TxStatus = RegInit(0.U(4.W)) //[14:11]
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val RxStatus = RegInit(0.U(2.W)) //[14:13]
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val TxStartFrm_wb = RegInit(false.B)
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// Synchronizing TxRetry TxDone_wb TxAbort signal (synchronized to WISHBONE clock)
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val TxRetry_wb = ShiftRegisters( io.TxRetry, 3, false.B, true.B )
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val TxAbort_wb = ShiftRegisters( io.TxAbort, 3, false.B, true.B )
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val TxDone_wb = ShiftRegisters( io.TxDone, 3, false.B, true.B )
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val TxRetryPacket = RegInit(false.B)
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val TxRetryPacket_NotCleared = RegInit(false.B)
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val TxDonePacket = RegInit(false.B)
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val TxDonePacket_NotCleared = RegInit(false.B)
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val TxAbortPacket = RegInit(false.B)
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val TxAbortPacket_NotCleared = RegInit(false.B)
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val RxBDReady = RegInit(false.B)
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val RxReady = RegInit(false.B)
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val TxBDReady = RegInit(false.B)
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val RxBDRead = RegInit(false.B)
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val BlockingTxStatusWrite = RegInit(false.B)
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val BlockingTxBDRead = RegInit(false.B)
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val RxBDAddress = RegInit(0.U(7.W)) //[7:1]
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val TxBDAddress = RegInit(0.U(7.W)) //[7:1]
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val ShiftEnded = RegInit(false.B)
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val RxOverrun = RegInit(false.B)
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val BDWrite = RegInit(0.U(4.W)) // BD Write Enable for access from WISHBONE side
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val BDRead = RegInit(false.B) // BD Read access from WISHBONE side
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val RxBDDataIn = Wire(UInt(32.W)) // Rx BD data in
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val TxBDDataIn = Wire(UInt(32.W)) // Tx BD data in
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val TxEndFrm_wb = RegInit(false.B)
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val TxRetryPulse = Wire(Bool())
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val TxDonePulse = Wire(Bool())
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val TxAbortPulse = Wire(Bool())
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val RxStatusWrite = Wire(Bool())
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val RxBufferFull = Wire(Bool())
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val RxBufferAlmostEmpty = Wire(Bool())
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val RxBufferEmpty = Wire(Bool())
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val BDAck = Reg(Bool());
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// Delayed stage signals
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val WbEn = RegInit(true.B)
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val WbEn_q = RegNext(WbEn, false.B)
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val RxEn = RegInit(false.B)
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val RxEn_q = RegNext(RxEn, false.B)
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val TxEn = RegInit(false.B)
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val TxEn_q = RegNext(TxEn, false.B)
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val r_TxEn_q = RegNext(io.r_TxEn, false.B)
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val r_RxEn_q = RegNext(io.r_RxEn, false.B)
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val ram_ce = true.B
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val ram_we = Wire(UInt(4.W))
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val ram_oe = Wire(Bool())
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val ram_addr = RegInit(0.U(8.W))
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val ram_di = RegInit(0.U(32.W))
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val ram_do = Wire(UInt(32.W))
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val txBuffDesc = ram_do.asTypeOf(new TxBuffDesc)
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val rxBuffDesc = ram_do.asTypeOf(new RxBuffDesc)
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val TxPointerRead = RegInit(false.B)
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val TxEn_needed = RegInit(false.B)
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val RxEn_needed = RegInit(false.B)
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val RxPointerRead = RegInit(false.B)
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// RX shift ending signals
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val ShiftEnded_rck_txclk = Wire(Bool())
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val ShiftEndedSync1 = RegNext( ShiftEnded_rck_txclk, false.B)
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val ShiftEndedSync2 = RegNext( ShiftEndedSync1, false.B)
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val ShiftEndedSync3 = RegInit(false.B)
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val StartOccured = RegInit(false.B)
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val TxStartFrm_sync_txclk = Wire(Bool())
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val TxStartFrm_syncb1 = RegNext(TxStartFrm_sync_txclk, false.B)
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val TxStartFrm_syncb2 = RegNext(TxStartFrm_syncb1, false.B)
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val TxFifoClear = Wire(Bool())
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val TxBufferAlmostFull = Wire(Bool())
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val TxBufferFull = Wire(Bool())
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val TxBufferEmpty = Wire(Bool())
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val TxBufferAlmostEmpty = Wire(Bool())
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val BlockReadTxDataFromMemory = RegInit(false.B)
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val TxData_wb = Wire(UInt(32.W))
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val ReadTxDataFromFifo_wb = Wire(Bool())
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val txfifo_cnt = Wire(UInt(5.W))
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val rxfifo_cnt = Wire(UInt(5.W))
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val ReadTxDataFromMemory = RegInit(false.B)
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val WriteRxDataToMemory = Wire(Bool())
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val MasterWbTX = RegInit(false.B)
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val MasterWbRX = RegInit(false.B)
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val TxPointerMSB = RegInit(0.U(30.W)) //[31:2]
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val TxPointerLSB = RegInit(0.U(2.W))
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val TxPointerLSB_rst = RegInit(0.U(2.W))
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val RxPointerMSB = RegInit(0.U(30.W)) //[31:2]
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val RxPointerLSB_rst = RegInit(0.U(2.W))
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val cyc_cleared = RegInit(false.B)
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val RxByteSel = Wire(UInt(4.W))
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// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
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val ReadTxDataFromFifo_tck_txclk = Wire(Bool())
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val ReadTxDataFromFifo_sync = ShiftRegisters( ReadTxDataFromFifo_tck_txclk, 3, false.B, true.B)
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val RxAbortLatched_rxclk = Wire(Bool())
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val RxAbortSync = ShiftRegisters( RxAbortLatched_rxclk, 4, false.B, true.B )
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val WriteRxDataToFifo_rxclk = Wire(Bool())
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val WriteRxDataToFifoSync = ShiftRegisters(WriteRxDataToFifo_rxclk, 3, false.B, true.B)
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val LatchedRxStartFrm_rxclk = Wire(Bool())
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val SyncRxStartFrm = ShiftRegisters(LatchedRxStartFrm_rxclk, 3, false.B, true.B)
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val RxStatusWriteLatched = RegInit(false.B)
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val RxStatusWriteLatched_syncb = ShiftRegister(io.RxStatusWriteLatched_sync2, 2, false.B, true.B)
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when(true.B){
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BDAck := (BDWrite.orR & WbEn & WbEn_q) | (BDRead & WbEn & ~WbEn_q)
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}
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// Generic synchronous single-port RAM interface
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val bd_ram = Module(new MacSRAM)
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val BD_WB_DAT_O = ram_do
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bd_ram.io.ce := ram_ce
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bd_ram.io.we := ram_we.asBools
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bd_ram.io.oe := ram_oe
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bd_ram.io.addr := ram_addr
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bd_ram.io.di := ram_di
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ram_do := bd_ram.io.dato
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ram_we :=
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(BDWrite & Fill(4,(WbEn & WbEn_q)) ) |
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Fill(4, (TxStatusWrite | RxStatusWrite) )
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ram_oe :=
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(BDRead & WbEn & WbEn_q) |
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(TxEn & TxEn_q & (TxBDRead | TxPointerRead)) |
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(RxEn & RxEn_q & (RxBDRead | RxPointerRead))
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when(~TxBDReady & io.r_TxEn & WbEn & ~WbEn_q){
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TxEn_needed := true.B
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} .elsewhen(TxPointerRead & TxEn & TxEn_q){
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TxEn_needed := false.B
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}
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// Enabling access to the RAM for three devices.
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val RAMAccessEnable =
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Cat(WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed)
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// Switching between three stages depends on enable signals
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when( RAMAccessEnable === BitPat("b1001?") ){ // synopsys parallel_case
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WbEn := false.B
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RxEn := true.B // wb access stage and r_RxEn is enabled
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TxEn := false.B
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ram_addr := Cat(RxBDAddress, RxPointerRead)
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ram_di := RxBDDataIn
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} .elsewhen( RAMAccessEnable === BitPat("b10001") ){
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WbEn := false.B
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RxEn := false.B
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TxEn := true.B // wb access stage, r_RxEn is disabled but r_TxEn is enabled
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ram_addr := Cat(TxBDAddress, TxPointerRead) //[7,1] + [0]
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ram_di := TxBDDataIn
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} .elsewhen( RAMAccessEnable === BitPat("b010?0") ){
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WbEn := true.B // RxEn access stage and r_TxEn is disabled
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RxEn := false.B
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TxEn := false.B
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ram_addr := io.tlSlv.A.bits.address(9,2) // [11:2 ] -> [9:2];
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ram_di := io.tlSlv.A.bits.data
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BDWrite := BDCs & Fill(4,(io.tlSlv.A.bits.opcode === 0.U) || (io.tlSlv.A.bits.opcode === 1.U))
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BDRead := BDCs.orR & (io.tlSlv.A.bits.opcode === 4.U)
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} .elsewhen( RAMAccessEnable === BitPat("b010?1") ){
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WbEn := false.B
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RxEn := false.B
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TxEn := true.B // RxEn access stage and r_TxEn is enabled
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ram_addr := Cat(TxBDAddress, TxPointerRead)
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ram_di := TxBDDataIn
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} .elsewhen( RAMAccessEnable === BitPat("b001??") ){
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WbEn := true.B // TxEn access stage (we always go to wb access stage)
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RxEn := false.B
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TxEn := false.B
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ram_addr := io.tlSlv.A.bits.address(9,2) //[11:2 ] ->[9:2]
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ram_di := io.tlSlv.A.bits.data
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BDWrite := BDCs & Fill(4,(io.tlSlv.A.bits.opcode === 0.U) || (io.tlSlv.A.bits.opcode === 1.U))
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BDRead := BDCs.orR & (io.tlSlv.A.bits.opcode === 4.U)
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} .elsewhen( RAMAccessEnable === BitPat("b10000") ){
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WbEn := false.B // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
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} .elsewhen( RAMAccessEnable === BitPat("b00000") ){
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WbEn := true.B // Idle state. We go to WbEn access stage.
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RxEn := false.B
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TxEn := false.B
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ram_addr := io.tlSlv.A.bits.address(9,2) // [11:2 ] -> [9:2]
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ram_di := io.tlSlv.A.bits.data
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BDWrite := BDCs & Fill(4,(io.tlSlv.A.bits.opcode === 0.U) || (io.tlSlv.A.bits.opcode === 1.U))
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BDRead := BDCs.orR & (io.tlSlv.A.bits.opcode === 4.U)
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}
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val ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse
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// Latching READY status of the Tx buffer descriptor
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when(TxEn & TxEn_q & TxBDRead){ // TxBDReady is sampled only once at the beginning.
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TxBDReady := txBuffDesc.rd & (txBuffDesc.len > 4.U)
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} .elsewhen(ResetTxBDReady){ // Only packets larger then 4 bytes are transmitted.
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TxBDReady := false.B
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}
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val StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady // Reading the Tx buffer descriptor
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when(StartTxBDRead){
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TxBDRead := true.B
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} .elsewhen(TxBDReady){
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TxBDRead := false.B
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}
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val StartTxPointerRead = TxBDRead & TxBDReady // Reading Tx BD pointer
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// Reading Tx BD Pointer
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when(StartTxPointerRead){
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TxPointerRead := true.B
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} .elsewhen(TxEn_q){
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TxPointerRead := false.B
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}
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// Writing status back to the Tx buffer descriptor
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TxStatusWrite := (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite
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// Status writing must occur only once. Meanwhile it is blocked.
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when(~TxDone_wb(1) & ~TxAbort_wb(1)){
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BlockingTxStatusWrite := false.B
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} .elsewhen(TxStatusWrite){
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BlockingTxStatusWrite := true.B
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}
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val BlockingTxStatusWrite_sync2_txclk = Wire(Bool())
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val BlockingTxStatusWrite_sync3_txclk = Wire(Bool())
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io.RstDeferLatched := BlockingTxStatusWrite_sync2_txclk & ~BlockingTxStatusWrite_sync3_txclk
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// TxBDRead state is activated only once.
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when(StartTxBDRead){
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BlockingTxBDRead := true.B
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} .elsewhen(~StartTxBDRead & ~TxBDReady){
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BlockingTxBDRead := false.B
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}
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// Latching status from the tx buffer descriptor Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
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when(TxEn & TxEn_q & TxBDRead){
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TxStatus := Cat(txBuffDesc.irq, txBuffDesc.wr, txBuffDesc.pad, txBuffDesc.crc)
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}
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//Latching length from the buffer descriptor;
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when(TxEn & TxEn_q & TxBDRead){
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TxLength := txBuffDesc.len
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}
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.elsewhen( MasterWbTX & io.tlMst.D.fire ){ //tx tileRead
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when( TxLength < 4.U ){
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TxLength := 0.U
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} .elsewhen(TxPointerLSB_rst === 0.U){
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TxLength := TxLength - 4.U // Length is subtracted at the data request
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} .elsewhen(TxPointerLSB_rst === 1.U){
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TxLength := TxLength - 3.U // Length is subtracted at the data request
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} .elsewhen(TxPointerLSB_rst === 2.U){
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TxLength := TxLength - 2.U // Length is subtracted at the data request
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} .elsewhen(TxPointerLSB_rst === 3.U){
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TxLength := TxLength - 1.U // Length is subtracted at the data request
|
|
}
|
|
}
|
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//Latching length from the buffer descriptor;
|
|
when(TxEn & TxEn_q & TxBDRead){
|
|
LatchedTxLength := txBuffDesc.len
|
|
}
|
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when(TxEn & TxEn_q & TxPointerRead){
|
|
TxPointerMSB := ram_do(31,2) // Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched because TxPointerMSB is only used for word-aligned accesses.
|
|
TxPointerLSB := ram_do(1,0) // Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed, valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This signals are used for proper selection of the star byte (TxData and TxByteCnt) are set by this two bits.
|
|
} .elsewhen( io.tlMst.D.fire & io.tlMst.D.bits.opcode === 1.U ){
|
|
TxPointerMSB := TxPointerMSB + 1.U // TxPointer is word-aligned
|
|
}
|
|
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|
|
|
// Latching 2 MSB bits of the buffer descriptor. After the read access, TxLength needs to be decremented for the number of the valid bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are valid so this two bits are reset to zero.
|
|
when(TxEn & TxEn_q & TxPointerRead){
|
|
TxPointerLSB_rst := ram_do(1,0)
|
|
} .elsewhen( MasterWbTX & io.tlMst.D.fire ){ // After first access pointer is word alligned
|
|
TxPointerLSB_rst := 0.U
|
|
}
|
|
|
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|
|
val isTlMstBusy = RegInit(false.B)
|
|
|
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|
|
when( (TxLength === 0.U) | TxAbortPulse | TxRetryPulse){
|
|
ReadTxDataFromMemory := false.B
|
|
} .elsewhen(TxEn & TxEn_q & TxPointerRead){
|
|
ReadTxDataFromMemory := true.B
|
|
}
|
|
|
|
val ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
|
|
|
|
when(
|
|
(TxBufferAlmostFull | TxLength <= 4.U) & MasterWbTX & isTlMstBusy & (~(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared))){
|
|
BlockReadTxDataFromMemory := true.B
|
|
} .elsewhen(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket){
|
|
BlockReadTxDataFromMemory := false.B
|
|
}
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TxFifoClear := (TxAbortPacket | TxRetryPacket)
|
|
|
|
val tx_fifo = Module( new MacFifo(dw = 32, dp = 16) )
|
|
tx_fifo.io.data_in := io.tlMst.D.bits.data
|
|
tx_fifo.io.write := io.tlMst.D.fire & io.tlMst.D.bits.opcode === 1.U
|
|
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|
|
tx_fifo.io.read := ReadTxDataFromFifo_wb & ~TxBufferEmpty
|
|
tx_fifo.io.clear := TxFifoClear
|
|
TxData_wb := tx_fifo.io.data_out
|
|
TxBufferFull := tx_fifo.io.full
|
|
TxBufferAlmostFull := tx_fifo.io.almost_full
|
|
TxBufferAlmostEmpty := tx_fifo.io.almost_empty
|
|
TxBufferEmpty := tx_fifo.io.empty
|
|
txfifo_cnt := tx_fifo.io.cnt
|
|
|
|
|
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|
|
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
|
|
when(TxBDReady & ~StartOccured & (TxBufferFull | TxLength === 0.U)){
|
|
TxStartFrm_wb := true.B
|
|
} .elsewhen(TxStartFrm_syncb2){
|
|
TxStartFrm_wb := false.B
|
|
}
|
|
|
|
|
|
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
|
|
when(TxStartFrm_wb){
|
|
StartOccured := true.B
|
|
} .elsewhen(ResetTxBDReady){
|
|
StartOccured := false.B
|
|
}
|
|
|
|
|
|
// TxEndFrm_wb: indicator of the end of frame
|
|
when((TxLength === 0.U) & TxBufferAlmostEmpty & io.TxUsedData){
|
|
TxEndFrm_wb := true.B
|
|
} .elsewhen(TxRetryPulse | TxDonePulse | TxAbortPulse){
|
|
TxEndFrm_wb := false.B
|
|
}
|
|
|
|
|
|
// Marks which bytes are valid within the word.
|
|
val TxValidBytes = Mux(TxLength < 4.U, TxLength(1,0), 0.U)
|
|
val TxValidBytesLatched = RegInit(0.U(2.W))
|
|
// val LatchValidBytes = RegNext((TxLength < 4.U) & TxBDReady, false.B)
|
|
// val LatchValidBytes_q = RegNext(LatchValidBytes, false.B)
|
|
|
|
val LatchValidBytes = ShiftRegisters((TxLength < 4.U) & TxBDReady, 2, false.B, true.B)
|
|
|
|
// Latching valid bytes
|
|
when(LatchValidBytes(0) & ~LatchValidBytes(1)){
|
|
TxValidBytesLatched := TxValidBytes
|
|
} .elsewhen(TxRetryPulse | TxDonePulse | TxAbortPulse){
|
|
TxValidBytesLatched := 0.U
|
|
}
|
|
|
|
|
|
// dontTouch(TxStatus)
|
|
val TxIRQEn = TxStatus.extract(3) //[14:11]
|
|
val WrapTxStatusBit = TxStatus.extract(2)
|
|
io.PerPacketPad := TxStatus.extract(1)
|
|
io.PerPacketCrcEn := TxStatus.extract(0)
|
|
|
|
val RxIRQEn = RxStatus.extract(1) //[14:13]
|
|
val WrapRxStatusBit = RxStatus.extract(0)
|
|
|
|
|
|
// Temporary Tx and Rx buffer descriptor address//[7:1]
|
|
val TempTxBDAddress = Mux( TxStatusWrite & ~WrapTxStatusBit, (TxBDAddress + 1.U), 0.U ) // Tx BD increment or wrap (last BD)
|
|
val TempRxBDAddress = Mux( WrapRxStatusBit, io.r_TxBDNum(6,0), (RxBDAddress + 1.U) ) // Using first Rx BD / Using next Rx BD
|
|
|
|
|
|
// Latching Tx buffer descriptor address
|
|
when(io.r_TxEn & (~r_TxEn_q)){
|
|
TxBDAddress := 0.U
|
|
} .elsewhen(TxStatusWrite){
|
|
TxBDAddress := TempTxBDAddress
|
|
}
|
|
|
|
// Latching Rx buffer descriptor address
|
|
when(io.r_RxEn & (~r_RxEn_q)){
|
|
RxBDAddress := io.r_TxBDNum(6,0)
|
|
} .elsewhen(RxStatusWrite){
|
|
RxBDAddress := TempRxBDAddress;
|
|
}
|
|
|
|
|
|
val TxStatusInLatched = Cat(io.TxUnderRun, io.RetryCntLatched, io.RetryLimit, io.LateCollLatched, io.DeferLatched, io.CarrierSenseLost)
|
|
val LatchedRxLength_rxclk = Wire(UInt(16.W))
|
|
val RxStatusInLatched_rxclk = Wire(UInt(9.W))
|
|
RxBDDataIn := Cat(LatchedRxLength_rxclk, 0.U(1.W), RxStatus, 0.U(4.W), RxStatusInLatched_rxclk)
|
|
TxBDDataIn := Cat(LatchedTxLength, 0.U(1.W), TxStatus, 0.U(2.W), TxStatusInLatched)
|
|
|
|
|
|
// Signals used for various purposes
|
|
TxRetryPulse := TxRetry_wb(1) & ~TxRetry_wb(2)
|
|
TxDonePulse := TxDone_wb(1) & ~TxDone_wb(2)
|
|
TxAbortPulse := TxAbort_wb(1) & ~TxAbort_wb(2)
|
|
|
|
val TxError = io.TxUnderRun | io.RetryLimit | io.LateCollLatched | io.CarrierSenseLost
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
val TxAbortPacketBlocked = RegInit(false.B)
|
|
|
|
when(
|
|
TxAbort_wb(1) & (~TxAbortPacketBlocked) & MasterWbTX & io.tlMst.D.fire & isLastD |
|
|
TxAbort_wb(1) & (~TxAbortPacketBlocked) & (~MasterWbTX) ){
|
|
TxAbortPacket := true.B
|
|
} .otherwise{
|
|
TxAbortPacket := false.B
|
|
}
|
|
|
|
|
|
when(TxEn & TxEn_q & TxAbortPacket_NotCleared){
|
|
TxAbortPacket_NotCleared := false.B
|
|
} .elsewhen(
|
|
TxAbort_wb(1) & (~TxAbortPacketBlocked) & MasterWbTX & io.tlMst.D.fire & isLastD |
|
|
TxAbort_wb(1) & (~TxAbortPacketBlocked) & (~MasterWbTX) ){
|
|
TxAbortPacket_NotCleared := true.B
|
|
}
|
|
|
|
when(~TxAbort_wb(1) & TxAbort_wb(2)){
|
|
TxAbortPacketBlocked := false.B
|
|
} .elsewhen(TxAbortPacket){
|
|
TxAbortPacketBlocked := true.B
|
|
}
|
|
|
|
|
|
|
|
val TxRetryPacketBlocked = RegInit(false.B)
|
|
|
|
when(
|
|
TxRetry_wb(1) & ~TxRetryPacketBlocked & MasterWbTX & io.tlMst.D.fire & isLastD |
|
|
TxRetry_wb(1) & ~TxRetryPacketBlocked & ~MasterWbTX ){
|
|
TxRetryPacket := true.B
|
|
} .otherwise{
|
|
TxRetryPacket := false.B
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
when(StartTxBDRead){
|
|
TxRetryPacket_NotCleared := false.B
|
|
} .elsewhen(
|
|
TxRetry_wb(1) & ~TxRetryPacketBlocked & MasterWbTX & io.tlMst.D.fire & isLastD |
|
|
TxRetry_wb(1) & ~TxRetryPacketBlocked & ~MasterWbTX ){
|
|
TxRetryPacket_NotCleared := true.B
|
|
}
|
|
|
|
|
|
when(~TxRetry_wb(1) & TxRetry_wb(2)){
|
|
TxRetryPacketBlocked := false.B
|
|
} .elsewhen(TxRetryPacket){
|
|
TxRetryPacketBlocked := true.B
|
|
}
|
|
|
|
|
|
|
|
val TxDonePacketBlocked = RegInit(false.B)
|
|
|
|
when(
|
|
TxDone_wb(1) & ~TxDonePacketBlocked & MasterWbTX & io.tlMst.D.fire & isLastD |
|
|
TxDone_wb(1) & ~TxDonePacketBlocked & ~MasterWbTX ){
|
|
TxDonePacket := true.B
|
|
}.otherwise{
|
|
TxDonePacket := false.B
|
|
}
|
|
|
|
when(TxEn & TxEn_q & TxDonePacket_NotCleared){
|
|
TxDonePacket_NotCleared := false.B
|
|
} .elsewhen(
|
|
TxDone_wb(1) & ~TxDonePacketBlocked & MasterWbTX & io.tlMst.D.fire & isLastD |
|
|
TxDone_wb(1) & ~TxDonePacketBlocked & ~MasterWbTX ){
|
|
TxDonePacket_NotCleared := true.B
|
|
}
|
|
|
|
|
|
when(~TxDone_wb(1) & TxDone_wb(2)){
|
|
TxDonePacketBlocked := false.B
|
|
} .elsewhen(TxDonePacket){
|
|
TxDonePacketBlocked := true.B
|
|
}
|
|
|
|
|
|
|
|
// Tx under run
|
|
when(TxAbortPulse){
|
|
TxUnderRun_wb := false.B
|
|
} .elsewhen(TxBufferEmpty & ReadTxDataFromFifo_wb){
|
|
TxUnderRun_wb := true.B
|
|
}
|
|
|
|
|
|
ReadTxDataFromFifo_wb := ReadTxDataFromFifo_sync(1) & ~ReadTxDataFromFifo_sync(2)
|
|
|
|
val StartRxBDRead = RxStatusWrite | (RxAbortSync(2) & ~RxAbortSync(3)) | (io.r_RxEn & ~r_RxEn_q)
|
|
|
|
// Reading the Rx buffer descriptor
|
|
when(StartRxBDRead & ~RxReady){
|
|
RxBDRead := true.B
|
|
} .elsewhen(RxBDReady){
|
|
RxBDRead := false.B
|
|
}
|
|
|
|
|
|
|
|
// Reading of the next receive buffer descriptor starts after reception status is written to the previous one.
|
|
|
|
// Latching READY status of the Rx buffer descriptor
|
|
when(RxPointerRead){
|
|
RxBDReady := false.B
|
|
} .elsewhen(RxEn & RxEn_q & RxBDRead){
|
|
RxBDReady := rxBuffDesc.e // RxBDReady is sampled only once at the beginning
|
|
}
|
|
|
|
|
|
// Latching Rx buffer descriptor status Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
|
|
when(RxEn & RxEn_q & RxBDRead){
|
|
RxStatus := Cat(rxBuffDesc.irq, rxBuffDesc.wrap)
|
|
}
|
|
|
|
|
|
|
|
// RxReady generation
|
|
when(ShiftEnded | RxAbortSync(1) & ~RxAbortSync(2) | ~io.r_RxEn & r_RxEn_q){
|
|
RxReady := false.B
|
|
} .elsewhen(RxEn & RxEn_q & RxPointerRead){
|
|
RxReady := true.B
|
|
}
|
|
|
|
// Reading Rx BD pointer
|
|
val StartRxPointerRead = RxBDRead & RxBDReady
|
|
|
|
// Reading Tx BD Pointer
|
|
when(StartRxPointerRead){
|
|
RxPointerRead := true.B
|
|
} .elsewhen(RxEn & RxEn_q){
|
|
RxPointerRead := false.B
|
|
}
|
|
|
|
|
|
|
|
//Latching Rx buffer pointer from buffer descriptor;
|
|
when(RxEn & RxEn_q & RxPointerRead){
|
|
RxPointerMSB := ram_do(31,2)
|
|
} .elsewhen(MasterWbRX & io.tlMst.A.fire ){
|
|
RxPointerMSB := RxPointerMSB + 1.U // Word access (always word access. m_wb_sel_o are used for selecting bytes)
|
|
}
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
|
when(MasterWbRX & io.tlMst.A.fire ){// After first write all RxByteSel are active
|
|
RxPointerLSB_rst := 0.U
|
|
} .elsewhen(RxEn & RxEn_q & RxPointerRead){
|
|
RxPointerLSB_rst := ram_do(1,0)
|
|
}
|
|
|
|
RxByteSel := Mux1H(Seq(
|
|
(RxPointerLSB_rst === 0.U) -> "hf".U,
|
|
(RxPointerLSB_rst === 1.U) -> "h7".U,
|
|
(RxPointerLSB_rst === 2.U) -> "h3".U,
|
|
(RxPointerLSB_rst === 3.U) -> "h1".U,
|
|
))
|
|
|
|
|
|
when(~RxReady & io.r_RxEn & WbEn & ~WbEn_q){
|
|
RxEn_needed := true.B
|
|
} .elsewhen(RxPointerRead & RxEn & RxEn_q){
|
|
RxEn_needed := false.B
|
|
}
|
|
|
|
|
|
|
|
// Reception status is written back to the buffer descriptor after the end of frame is detected.
|
|
RxStatusWrite := ShiftEnded & RxEn & RxEn_q
|
|
|
|
|
|
|
|
|
|
val LastByteIn_rxclk = Wire(Bool())
|
|
val RxByteCnt_rxclk = Wire(UInt(2.W))
|
|
val RxEnableWindow_rxclk = Wire(Bool())
|
|
val StartShiftWillEnd = LastByteIn_rxclk | io.RxValid & io.RxEndFrm & RxByteCnt_rxclk.andR & RxEnableWindow_rxclk
|
|
|
|
// Indicating start of the reception process
|
|
val ShiftWillEnd_rxclk = Wire(Bool())
|
|
val SetWriteRxDataToFifo =
|
|
(io.RxValid & RxReady & ~io.RxStartFrm & RxEnableWindow_rxclk & (RxByteCnt_rxclk.andR)) |
|
|
(io.RxValid & RxReady & io.RxStartFrm & (RxPointerLSB_rst.andR)) |
|
|
(ShiftWillEnd_rxclk & LastByteIn_rxclk & (RxByteCnt_rxclk.andR))
|
|
|
|
|
|
val WriteRxDataToFifo_wb = WriteRxDataToFifoSync(1) & ~WriteRxDataToFifoSync(2)
|
|
val RxFifoReset = SyncRxStartFrm(1) & ~SyncRxStartFrm(2)
|
|
|
|
val rx_fifo = Module(new MacFifo(dw = 32, dp = 16))
|
|
val RxDataLatched2_rxclk = Wire(UInt(32.W))
|
|
rx_fifo.io.data_in := RxDataLatched2_rxclk
|
|
rx_fifo.io.write := WriteRxDataToFifo_wb & ~RxBufferFull
|
|
rx_fifo.io.read := MasterWbRX & io.tlMst.A.fire
|
|
rx_fifo.io.clear := RxFifoReset
|
|
|
|
|
|
|
|
RxBufferFull := rx_fifo.io.full
|
|
RxBufferAlmostEmpty := rx_fifo.io.almost_empty
|
|
RxBufferEmpty := rx_fifo.io.empty
|
|
rxfifo_cnt := rx_fifo.io.cnt
|
|
|
|
|
|
|
|
|
|
|
|
WriteRxDataToMemory := ~RxBufferEmpty
|
|
|
|
|
|
|
|
|
|
|
|
when(ShiftEndedSync1 & ~ShiftEndedSync2){
|
|
ShiftEndedSync3 := true.B
|
|
} .elsewhen(ShiftEnded){
|
|
ShiftEndedSync3 := false.B
|
|
}
|
|
|
|
|
|
// Generation of the end-of-frame signal
|
|
when(ShiftEndedSync3 & MasterWbRX & io.tlMst.A.fire & RxBufferAlmostEmpty & ~ShiftEnded){
|
|
ShiftEnded := true.B
|
|
} .elsewhen(RxStatusWrite){
|
|
ShiftEnded := false.B
|
|
}
|
|
|
|
|
|
|
|
|
|
val RxStatusIn = Cat(io.ReceivedPauseFrm, io.AddressMiss, RxOverrun, io.InvalidSymbol, io.DribbleNibble, io.ReceivedPacketTooBig, io.ShortFrame, io.LatchedCrcError, io.RxLateCollision)
|
|
|
|
|
|
// Rx overrun
|
|
when(RxStatusWrite){
|
|
RxOverrun := false.B
|
|
} .elsewhen(RxBufferFull & WriteRxDataToFifo_wb){
|
|
RxOverrun := true.B
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames are aborted when signal r_RecSmall is set to 0 in MODER register.
|
|
// AddressMiss is identifying that a frame was received because of the promiscous mode and is not an error
|
|
val RxError = (RxStatusInLatched_rxclk(6,3).orR) | (RxStatusInLatched_rxclk(1,0).orR)
|
|
|
|
|
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
|
|
when(RxStatusWriteLatched_syncb){
|
|
RxStatusWriteLatched := false.B
|
|
} .elsewhen(RxStatusWrite){
|
|
RxStatusWriteLatched := true.B
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Tx Done Interrupt
|
|
when(TxStatusWrite & TxIRQEn){
|
|
TxB_IRQ := ~TxError
|
|
} .otherwise{
|
|
TxB_IRQ := false.B
|
|
}
|
|
|
|
// Tx Error Interrupt
|
|
when(TxStatusWrite & TxIRQEn){
|
|
TxE_IRQ := TxError
|
|
} .otherwise{
|
|
TxE_IRQ := false.B
|
|
}
|
|
|
|
// Rx Done Interrupt
|
|
when(RxStatusWrite & RxIRQEn & io.ReceivedPacketGood & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & io.r_PassAll & (~io.r_RxFlow))){
|
|
RxB_IRQ := (~RxError)
|
|
} .otherwise{
|
|
RxB_IRQ := false.B
|
|
}
|
|
|
|
// Rx Error Interrupt
|
|
when(RxStatusWrite & RxIRQEn & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & io.r_PassAll & (~io.r_RxFlow))){
|
|
RxE_IRQ := RxError
|
|
} .otherwise{
|
|
RxE_IRQ := false.B
|
|
}
|
|
|
|
|
|
|
|
|
|
// Busy Interrupt
|
|
val Busy_IRQ_rck_rxclk = Wire(Bool())
|
|
val Busy_IRQ_sync = ShiftRegisters(Busy_IRQ_rck_rxclk, 3)
|
|
|
|
|
|
io.Busy_IRQ := Busy_IRQ_sync(1) & ~Busy_IRQ_sync(2)
|
|
|
|
|
|
|
|
// Connected to registers
|
|
// val CsMiss = Wire(Bool())
|
|
|
|
|
|
|
|
|
|
BDCs := Fill(4, io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & io.tlSlv.A.bits.address(10)) & io.tlSlv.A.bits.mask // 0x400 - 0x7FF
|
|
// CsMiss := io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & io.tlSlv.A.bits.address(11) // 0x800 - 0xfFF // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid.
|
|
|
|
val slvAInfo = RegEnable( io.tlSlv.A.bits, io.tlSlv.A.fire )
|
|
val slvDValid = RegInit(false.B); io.tlSlv.D.valid := slvDValid
|
|
val slvDDat = Reg(UInt(32.W))
|
|
|
|
|
|
|
|
when( io.tlSlv.D.fire ){
|
|
slvDValid := false.B
|
|
} .elsewhen(io.tlSlv.A.fire){
|
|
slvDValid := true.B
|
|
slvDDat := BD_WB_DAT_O
|
|
}
|
|
|
|
when(slvAInfo.opcode === 4.U) {
|
|
io.tlSlv.D.bits := edgeIn.AccessAck(slvAInfo, slvDDat)
|
|
} .otherwise {
|
|
io.tlSlv.D.bits := edgeIn.AccessAck(slvAInfo)
|
|
}
|
|
|
|
io.tlSlv.A.ready := BDAck
|
|
assert( ~(io.tlSlv.A.ready & ~io.tlSlv.A.valid) )
|
|
|
|
// when( io.tlSlv.A.fire & (~(io.tlSlv.A.bits.mask.orR) | CsMiss) ){
|
|
// assert( false.B, "Assert Failed, tileLink access an undefine region!" )
|
|
// }
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
val mstAValid = RegInit(false.B)
|
|
val mstABits = Reg(new TLBundleA(edgeOut.bundle))
|
|
|
|
|
|
|
|
// val tlMstStateDnxt = WireDefault()
|
|
// val tlMstState = RegNext( )
|
|
|
|
|
|
|
|
when( io.tlMst.A.fire ){
|
|
mstAValid := false.B
|
|
}
|
|
.elsewhen( MasterWbRX & ~isTlMstBusy ) {
|
|
mstAValid := true.B
|
|
mstABits :=
|
|
edgeOut.Put(
|
|
fromSource = 0.U,
|
|
toAddress = RxPointerMSB << 2,
|
|
lgSize = log2Ceil(32/8).U,
|
|
data = rx_fifo.io.data_out,
|
|
mask = RxByteSel,
|
|
)._2
|
|
}
|
|
.elsewhen( MasterWbTX & ~isTlMstBusy ){
|
|
mstAValid := true.B
|
|
mstABits :=
|
|
edgeOut.Get(
|
|
fromSource = 0.U,
|
|
toAddress = TxPointerMSB << 2,
|
|
lgSize = log2Ceil(32/8).U,
|
|
)._2
|
|
}
|
|
|
|
when( io.tlMst.A.fire ){
|
|
isTlMstBusy := true.B
|
|
} .elsewhen( io.tlMst.D.fire ){
|
|
isTlMstBusy := false.B
|
|
}
|
|
|
|
when( ~MasterWbTX & ~MasterWbRX ){
|
|
when( WriteRxDataToMemory ){
|
|
MasterWbRX := true.B
|
|
} .elsewhen(ReadTxDataFromMemory_2) {
|
|
MasterWbTX := true.B
|
|
}
|
|
} .elsewhen( ~MasterWbTX & MasterWbRX){ //1.4A + 1D fifo to memory
|
|
when( io.tlMst.D.fire & isLastD & ~WriteRxDataToMemory ){
|
|
MasterWbRX := false.B
|
|
}
|
|
} .elsewhen( MasterWbTX & ~MasterWbRX){ //1 A + 1.4D memory to fifo
|
|
when( io.tlMst.D.fire & isLastD & ~ReadTxDataFromMemory_2 ){
|
|
MasterWbTX := false.B
|
|
}
|
|
}
|
|
|
|
|
|
when(io.tlMst.D.fire & io.tlMst.D.bits.opcode === 1.U) { assert( MasterWbTX ) }
|
|
when(io.tlMst.D.fire & io.tlMst.D.bits.opcode === 0.U) { assert( MasterWbRX ) }
|
|
|
|
|
|
val tlMstAValid_dbg = RegInit(true.B)
|
|
io.tlMst.A.valid := mstAValid & tlMstAValid_dbg
|
|
io.tlMst.A.bits := mstABits
|
|
|
|
|
|
val tlMstDReady = RegInit(true.B)
|
|
|
|
dontTouch(tlMstDReady)
|
|
dontTouch(tlMstAValid_dbg)
|
|
io.tlMst.D.ready := tlMstDReady
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
trait MacTileLinkTXClk{ this: MacTileLinkBase =>
|
|
withClockAndReset( io.MTxClk.asClock, reset.asAsyncReset ) {
|
|
|
|
val Flop = RegInit(false.B)
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
|
val BlockingTxStatusWrite_sync1 = RegNext(BlockingTxStatusWrite, false.B)
|
|
val BlockingTxStatusWrite_sync2 = RegNext(BlockingTxStatusWrite_sync1, false.B); BlockingTxStatusWrite_sync2_txclk := BlockingTxStatusWrite_sync2
|
|
val BlockingTxStatusWrite_sync3 = RegNext(BlockingTxStatusWrite_sync2, false.B); BlockingTxStatusWrite_sync3_txclk := BlockingTxStatusWrite_sync3
|
|
|
|
// Synchronizing TxStartFrm_wb to MTxClk
|
|
val TxStartFrm_sync = ShiftRegister( TxStartFrm_wb, 2, false.B, true.B ); TxStartFrm_sync_txclk := TxStartFrm_sync
|
|
|
|
val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm
|
|
val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
|
|
val TxData = RegInit(0.U(8.W)); io.TxData := TxData
|
|
val TxUnderRun = RegInit(false.B); io.TxUnderRun := TxUnderRun
|
|
val TxDataLatched = RegInit(0.U(32.W))
|
|
val TxByteCnt = RegInit(0.U(2.W))
|
|
val LastWord = RegInit(false.B)
|
|
val ReadTxDataFromFifo_tck = RegInit(false.B); ReadTxDataFromFifo_tck_txclk := ReadTxDataFromFifo_tck
|
|
|
|
// Generating delayed signals
|
|
val TxAbort_q = RegNext( io.TxAbort, false.B)
|
|
val TxRetry_q = RegNext( io.TxRetry, false.B)
|
|
val TxUsedData_q = RegNext( io.TxUsedData, false.B)
|
|
|
|
val ReadTxDataFromFifo_syncb = ShiftRegisters(ReadTxDataFromFifo_sync(1), 3, false.B, true.B)
|
|
|
|
// Changes for tx occur every second clock. Flop is used for this manner.
|
|
when( io.TxDone | io.TxAbort | TxRetry_q){
|
|
Flop := false.B
|
|
} .elsewhen ( io.TxUsedData ){
|
|
Flop := ~Flop
|
|
}
|
|
|
|
when(TxStartFrm_sync){
|
|
TxStartFrm := true.B
|
|
} .elsewhen(TxUsedData_q | ~TxStartFrm_sync & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){
|
|
TxStartFrm := false.B
|
|
}
|
|
|
|
|
|
// Indication of the last word
|
|
when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
|
|
LastWord := false.B
|
|
} .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){
|
|
LastWord := TxEndFrm_wb
|
|
}
|
|
|
|
// Tx end frame generation
|
|
when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){
|
|
TxEndFrm := false.B
|
|
} .elsewhen(Flop & LastWord){
|
|
TxEndFrm :=
|
|
Mux1H(Seq(
|
|
(TxValidBytesLatched === 1.U) -> (TxByteCnt === 0.U),
|
|
(TxValidBytesLatched === 2.U) -> (TxByteCnt === 1.U),
|
|
(TxValidBytesLatched === 3.U) -> (TxByteCnt === 2.U),
|
|
(TxValidBytesLatched === 0.U) -> (TxByteCnt === 3.U),
|
|
))
|
|
}
|
|
|
|
|
|
|
|
// Tx data selection (latching)
|
|
when( TxStartFrm_sync & ~TxStartFrm ){
|
|
TxData := Mux1H(Seq(
|
|
( TxPointerLSB === 0.U ) -> TxData_wb(31,24),// Big Endian Byte Ordering
|
|
( TxPointerLSB === 1.U ) -> TxData_wb(23,16),// Big Endian Byte Ordering
|
|
( TxPointerLSB === 2.U ) -> TxData_wb(15, 8),// Big Endian Byte Ordering
|
|
( TxPointerLSB === 3.U ) -> TxData_wb( 7, 0),// Big Endian Byte Ordering
|
|
))
|
|
} .elsewhen( TxStartFrm & io.TxUsedData & TxPointerLSB === 3.U ){
|
|
TxData := TxData_wb(31,24) // Big Endian Byte Ordering
|
|
} .elsewhen(io.TxUsedData & Flop){
|
|
TxData := Mux1H(Seq(
|
|
(TxByteCnt === 0.U) -> TxDataLatched(31,24),// Big Endian Byte Ordering
|
|
(TxByteCnt === 1.U) -> TxDataLatched(23,16),
|
|
(TxByteCnt === 2.U) -> TxDataLatched(15, 8),
|
|
(TxByteCnt === 3.U) -> TxDataLatched( 7, 0),
|
|
))
|
|
}
|
|
|
|
|
|
|
|
// Latching tx data
|
|
when(
|
|
TxStartFrm_sync & ~TxStartFrm |
|
|
io.TxUsedData & Flop & TxByteCnt === 3.U |
|
|
TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){
|
|
TxDataLatched := TxData_wb
|
|
}
|
|
|
|
|
|
val TxUnderRun_sync1 = RegInit(false.B)
|
|
|
|
// Tx under run
|
|
when(TxUnderRun_wb){
|
|
TxUnderRun_sync1 := true.B
|
|
} .elsewhen(BlockingTxStatusWrite_sync2){
|
|
TxUnderRun_sync1 := false.B
|
|
}
|
|
|
|
|
|
// Tx under run
|
|
when(BlockingTxStatusWrite_sync2){
|
|
TxUnderRun := false.B
|
|
} .elsewhen(TxUnderRun_sync1){
|
|
TxUnderRun := true.B
|
|
}
|
|
|
|
|
|
|
|
// Tx Byte counter
|
|
when(TxAbort_q | TxRetry_q){
|
|
TxByteCnt := 0.U
|
|
} .elsewhen(TxStartFrm & ~io.TxUsedData){
|
|
TxByteCnt := Mux1H(Seq(
|
|
( TxPointerLSB === 0.U ) -> 1.U,
|
|
( TxPointerLSB === 1.U ) -> 2.U,
|
|
( TxPointerLSB === 2.U ) -> 3.U,
|
|
( TxPointerLSB === 3.U ) -> 0.U,
|
|
))
|
|
} .elsewhen(io.TxUsedData & Flop){
|
|
TxByteCnt := TxByteCnt + 1.U
|
|
}
|
|
|
|
when(TxStartFrm_sync & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U &
|
|
~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){
|
|
ReadTxDataFromFifo_tck := true.B
|
|
} .elsewhen(ReadTxDataFromFifo_syncb(1) & ~ReadTxDataFromFifo_syncb(2)){
|
|
ReadTxDataFromFifo_tck := false.B
|
|
}
|
|
|
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
trait MacTileLinkRXClk{ this: MacTileLinkBase =>
|
|
|
|
withClockAndReset( io.MRxClk.asClock, reset.asAsyncReset ){
|
|
|
|
val RxDataLatched2 = RegInit(0.U(32.W)); RxDataLatched2_rxclk := RxDataLatched2
|
|
val RxDataLatched1 = RegInit(0.U(24.W)) // Big Endian Byte Ordering[31:8]
|
|
val RxValidBytes = RegInit(1.U(2.W))
|
|
val RxByteCnt = RegInit(0.U(2.W)); RxByteCnt_rxclk := RxByteCnt
|
|
val LastByteIn = RegInit(false.B); LastByteIn_rxclk := LastByteIn
|
|
val ShiftWillEnd = RegInit(false.B); ShiftWillEnd_rxclk := ShiftWillEnd
|
|
val WriteRxDataToFifo = RegInit(false.B); WriteRxDataToFifo_rxclk := WriteRxDataToFifo
|
|
val RxAbortLatched = RegInit(false.B); RxAbortLatched_rxclk := RxAbortLatched
|
|
|
|
val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); LatchedRxLength_rxclk := LatchedRxLength
|
|
val RxStatusInLatched = RegEnable(RxStatusIn, 0.U(9.W), io.LoadRxStatus); RxStatusInLatched_rxclk := RxStatusInLatched
|
|
val ShiftEnded_rck = RegInit(false.B); ShiftEnded_rck_txclk := ShiftEnded_rck
|
|
|
|
val ShiftEndedSync = ShiftRegisters(ShiftEndedSync2, 2, false.B, true.B)
|
|
|
|
val RxAbortSyncb = ShiftRegister( RxAbortSync(1), 2, false.B, true.B )
|
|
|
|
val RxEnableWindow = RegInit(false.B); RxEnableWindow_rxclk := RxEnableWindow
|
|
val LatchedRxStartFrm = RegInit(false.B); LatchedRxStartFrm_rxclk := LatchedRxStartFrm
|
|
|
|
val RxStatusWriteLatched_sync = ShiftRegister(RxStatusWriteLatched, 2, false.B, true.B); io.RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync
|
|
// Indicating that last byte is being reveived
|
|
|
|
when(ShiftWillEnd & RxByteCnt.andR | io.RxAbort){
|
|
LastByteIn := false.B
|
|
} .elsewhen(io.RxValid & RxReady & io.RxEndFrm & ~(RxByteCnt.andR) & RxEnableWindow){
|
|
LastByteIn := true.B
|
|
}
|
|
|
|
// Indicating that data reception will end
|
|
when(ShiftEnded_rck | io.RxAbort){
|
|
ShiftWillEnd := false.B
|
|
} .elsewhen(StartShiftWillEnd){
|
|
ShiftWillEnd := true.B
|
|
}
|
|
|
|
// Receive byte counter
|
|
when(ShiftEnded_rck | io.RxAbort){
|
|
RxByteCnt := 0.U
|
|
} .elsewhen(io.RxValid & io.RxStartFrm & RxReady){
|
|
RxByteCnt := Mux1H(Seq(
|
|
( RxPointerLSB_rst === 0.U ) -> 1.U,
|
|
( RxPointerLSB_rst === 1.U ) -> 2.U,
|
|
( RxPointerLSB_rst === 2.U ) -> 3.U,
|
|
( RxPointerLSB_rst === 3.U ) -> 0.U,
|
|
))
|
|
} .elsewhen(io.RxValid & RxEnableWindow & RxReady | LastByteIn){
|
|
RxByteCnt := RxByteCnt + 1.U
|
|
}
|
|
|
|
// Indicates how many bytes are valid within the last word
|
|
when(io.RxValid & io.RxStartFrm){
|
|
RxValidBytes := Mux1H(Seq(
|
|
( RxPointerLSB_rst === 0.U ) -> 1.U,
|
|
( RxPointerLSB_rst === 1.U ) -> 2.U,
|
|
( RxPointerLSB_rst === 2.U ) -> 3.U,
|
|
( RxPointerLSB_rst === 3.U ) -> 0.U,
|
|
))
|
|
} .elsewhen(io.RxValid & ~LastByteIn & ~io.RxStartFrm & RxEnableWindow){
|
|
RxValidBytes := RxValidBytes + 1.U
|
|
}
|
|
|
|
when(io.RxValid & RxReady & ~LastByteIn){
|
|
when(io.RxStartFrm){
|
|
RxDataLatched1 := Mux1H(Seq(
|
|
( RxPointerLSB_rst === 0.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),// Big Endian Byte Ordering
|
|
( RxPointerLSB_rst === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)),
|
|
( RxPointerLSB_rst === 2.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),
|
|
( RxPointerLSB_rst === 3.U ) -> RxDataLatched1,
|
|
))
|
|
} .elsewhen(RxEnableWindow){
|
|
RxDataLatched1 := Mux1H(Seq(
|
|
( RxByteCnt === 0.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),// Big Endian Byte Ordering
|
|
( RxByteCnt === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)),
|
|
( RxByteCnt === 2.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),
|
|
( RxByteCnt === 3.U ) -> RxDataLatched1,
|
|
))
|
|
}
|
|
}
|
|
|
|
|
|
// Assembling data that will be written to the rx_fifo
|
|
when(SetWriteRxDataToFifo & ~ShiftWillEnd){
|
|
RxDataLatched2 := Cat(RxDataLatched1, io.RxData)// Big Endian Byte Ordering
|
|
} .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){
|
|
RxDataLatched2 := Mux1H(Seq(
|
|
( RxValidBytes === 0.U ) -> Cat(RxDataLatched1, io.RxData),
|
|
( RxValidBytes === 1.U ) -> Cat(RxDataLatched1(23,16), 0.U(24.W)),
|
|
( RxValidBytes === 2.U ) -> Cat(RxDataLatched1(23, 8), 0.U(16.W)),
|
|
( RxValidBytes === 3.U ) -> Cat(RxDataLatched1, 0.U(8.W)),
|
|
))
|
|
}
|
|
|
|
when(SetWriteRxDataToFifo & ~io.RxAbort){
|
|
WriteRxDataToFifo := true.B
|
|
} .elsewhen(WriteRxDataToFifoSync(1) | io.RxAbort){
|
|
WriteRxDataToFifo := false.B
|
|
}
|
|
|
|
|
|
when(io.RxStartFrm & ~SyncRxStartFrm(1)){
|
|
LatchedRxStartFrm := true.B
|
|
} .elsewhen(SyncRxStartFrm(1)){
|
|
LatchedRxStartFrm := false.B
|
|
}
|
|
|
|
|
|
// Generation of the end-of-frame signal
|
|
when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){
|
|
ShiftEnded_rck := true.B
|
|
} .elsewhen(io.RxAbort | ShiftEndedSync(0) & ShiftEndedSync(1)){
|
|
ShiftEnded_rck := false.B
|
|
}
|
|
|
|
// Generation of the end-of-frame signal
|
|
when(io.RxStartFrm){
|
|
RxEnableWindow := true.B
|
|
} .elsewhen(io.RxEndFrm | io.RxAbort){
|
|
RxEnableWindow := false.B
|
|
}
|
|
|
|
|
|
when(RxAbortSyncb){
|
|
RxAbortLatched := false.B
|
|
} .elsewhen(io.RxAbort){
|
|
RxAbortLatched := true.B
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
val Busy_IRQ_rck = RegInit(false.B); Busy_IRQ_rck_rxclk := Busy_IRQ_rck
|
|
val Busy_IRQ_syncb = ShiftRegister( Busy_IRQ_sync(1), 2, false.B, true.B )
|
|
|
|
when(io.RxValid & io.RxStartFrm & ~RxReady){
|
|
Busy_IRQ_rck := true.B
|
|
} .elsewhen(Busy_IRQ_syncb){
|
|
Busy_IRQ_rck := false.B
|
|
}
|
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}
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}
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class MacTileLink(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends MacTileLinkBase(edgeIn, edgeOut) with MacTileLinkTXClk with MacTileLinkRXClk
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