diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/mac/MacTilelink.scala
index 1380e3c..1a99cd7 100644
--- a/src/main/scala/mac/MacTilelink.scala
+++ b/src/main/scala/mac/MacTilelink.scala
@@ -1140,7 +1140,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
 
 trait MacTileLinkTXClk{ this: MacTileLinkBase =>
-  withClockAndReset( io.MTxClk.asClock, reset ) {
+  withClockAndReset( io.MTxClk.asClock, reset.asAsyncReset ) {
 
     val Flop = RegInit(false.B)
     // Synchronizing BlockingTxStatusWrite to MTxClk
@@ -1313,7 +1313,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
 
 trait MacTileLinkRXClk{ this: MacTileLinkBase =>
 
-  withClockAndReset( io.MRxClk.asClock, reset ){
+  withClockAndReset( io.MRxClk.asClock, reset.asAsyncReset ){
 
     val RxDataLatched2 = RegInit(0.U(32.W)); RxDataLatched2_rxclk := RxDataLatched2
     val RxDataLatched1 = RegInit(0.U(24.W))     // Big Endian Byte Ordering[31:8] 
diff --git a/src/main/scala/mac/Rocket/RocketMac.scala b/src/main/scala/mac/Rocket/RocketMac.scala
deleted file mode 100644
index 2795b3c..0000000
--- a/src/main/scala/mac/Rocket/RocketMac.scala
+++ /dev/null
@@ -1,35 +0,0 @@
-// package Top
-
-// import chisel3._
-// import Mac._
-
-
-// import freechips.rocketchip.system._
-// import org.chipsalliance.cde.config.Parameters
-// import freechips.rocketchip.subsystem._
-// import freechips.rocketchip.devices.tilelink._
-// import freechips.rocketchip.util.DontTouch
-
-
-
-// /** Example Top with periphery devices and ports, and a Rocket subsystem */
-// class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem
-//     with HasAsyncExtInterrupts
-//     with CanHaveMasterAXI4MemPort
-//     with CanHaveMasterAXI4MMIOPort
-//     with CanHaveSlaveAXI4Port
-//     with WithManyMacMix
-// {
-//   // optionally add ROM devices
-//   // Note that setting BootROMLocated will override the reset_vector for all tiles
-//   val bootROM  = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
-//   val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
-
-//   override lazy val module = new ExampleRocketSystemModuleImp(this)
-// }
-
-// class ExampleRocketSystemModuleImp[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModuleImp(_outer)
-//     with HasRTCModuleImp
-//     with HasExtInterruptsModuleImp
-//     with DontTouch
-