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bugfix: spisel的写入位宽扩大到3bit

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RuigeLee
2026-02-09 14:47:29 +08:00
parent 9d01b626d2
commit 40f559024f
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/backBoard/shin/Interface.scala
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@@ -620,7 +620,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U )
cReg.spiSel := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U )
cReg.spiSel := RegEnable( dataw(2,0), 1.U(3.W), isEnW & addrw === "h9".U )
mReg.txSM := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U )
mReg.rxSM := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )