diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 7717337..58671b2 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -620,7 +620,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
   
   cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U )
-  cReg.spiSel  := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U )
+  cReg.spiSel  := RegEnable( dataw(2,0), 1.U(3.W), isEnW & addrw === "h9".U )
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )