From 40f559024f883f50be4bac038d859f40a725a0fa Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Mon, 9 Feb 2026 14:47:29 +0800 Subject: [PATCH] =?UTF-8?q?bugfix:=20spisel=E7=9A=84=E5=86=99=E5=85=A5?= =?UTF-8?q?=E4=BD=8D=E5=AE=BD=E6=89=A9=E5=A4=A7=E5=88=B03bit?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 7717337..58671b2 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -620,7 +620,7 @@ trait InterfaceMCUop{ this: InterfaceBase => cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U ) - cReg.spiSel := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U ) + cReg.spiSel := RegEnable( dataw(2,0), 1.U(3.W), isEnW & addrw === "h9".U ) mReg.txSM := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U ) mReg.rxSM := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )