准备编译

src/main/scala/backBoard/shin/SMUnit.scala

@@ -61,31 +61,29 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
   }
 
   for( i <- 0 until depth ){
-    io.sram(i).addrw := 0.U
-    io.sram(i).dataw := 0.U
-    io.sram(i).enw   := false.B
+    io.sram(i).wr.addrw := 0.U
+    io.sram(i).wr.dataw := 0.U
+    io.sram(i).wr.enw   := false.B
 
-    io.sram(i).addrr := 0.U
-    io.sram(i).enr   := false.B
+    io.sram(i).rd.addrr := 0.U
+    io.sram(i).rd.enr   := false.B
   }
 
   for( i <- 0 until depth ){
     when( wPtr === i.U & ~isFull ){
-      io.sram(i).addrw := io.sram_w.addrw
-      io.sram(i).dataw := io.sram_w.dataw
-      io.sram(i).enw   := io.sram_w.enw
+      io.sram(i).wr <> io.sram_w.addrw
     }
 
     when( rPtr === i.U & ~isEmpty){
-      io.sram(i).addrr := io.sram_r.addrr
-      io.sram(i).enr   := io.sram_r.enr
+      io.sram(i).rd.addrr := io.sram_r.addrr
+      io.sram(i).rd.enr   := io.sram_r.enr
     }
   }
 
 
 
   io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
-    ( rPtr === i.U ) -> io.sram(i).datar,
+    ( rPtr === i.U ) -> io.sram(i).rd.datar
   })