diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 44dc1e5..1198922 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -3,9 +3,7 @@ package BACK
 import chisel3._
 import chisel3.util._
 
-class InterfaceIO extends Module{
 
-}
 
 class MasterRegisterBundle extends Bundle{
   val isMstNSlv = Bool()
@@ -47,6 +45,84 @@ class MasterRegisterBundle extends Bundle{
 }
 
 
+class SlaveRegisterBundle extends Bundle{
+  val isMstNSlv = Bool()
+  val hwVersion = UInt(8.W)
+  val hwSerial  = UInt(48.W)
+  val busRate   = UInt(16.W)
+
+  val RAMSize   = UInt(8.W)
+  val MMUNum    = UInt(8.W)
+
+  val nodeSeqAddr = UInt(16.W)
+  val nodeSetAddr = UInt(16.W)
+
+  val spiSel       = UInt(2.W)
+
+  val isSoftReset  = Bool()
+  val encryptKey   = UInt(128.W)
+  val isEncrypt    = Bool()
+
+  val ebmmu = Vec(8, new Bundle{
+    val logicAddr = UInt(32.W)
+    val length = UInt(16.W)
+    val phyAddr = UInt(32.W)
+    val op = UInt(2.W)
+    val enable = Bool()
+  })
+
+  val intStatus = UInt(16.W)
+  val mb = Vec(8, new Bundle{
+    val ctrl = UInt(8.W)
+    val status = UInt(8.W)
+  })
+
+  val upRecErrorCnt   = UInt(32.W)
+  val downRecErrorCnt = UInt(32.W)
+
+  val upForwardErrorCnt   = UInt(32.W)
+  val downForwardErrorCnt = UInt(32.W)
+
+  val qspiErrorCnt   = UInt(32.W)
+  val forwardCnt     = UInt(32.W)
+  val recByteCnt     = UInt(32.W)
+  val forwardByteCnt = UInt(32.W)
+
+  val linkStatus = UInt(8.W)
+
+  val wdtStatus   = UInt(16.W)
+  val wdtOverflow = UInt(8.W)
+
+  val timeStamp = UInt(64.W)
+  val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器 
+  val upTimeStamp   = UInt(64.W) //上行本地时间戳寄存器
+  val mstTimeStamp  = UInt(64.W) //主站时间戳
+  val deltaTime = UInt(32.W)
+
+  val dcSyncEnable = Bool()
+  val dcSyncWidth  = UInt(16.W)
+}
+
+class SPIInterfaceIO extends Bundle{
+  val sck  = Input(Bool())
+  val csn  = Input(Bool())
+  val mosi = Input(Bool())
+  val miso = Output(Bool())
+}
+
+class InterfaceIO extends Bundle{
+  val spi = new SPIInterfaceIO
+
+  val req = Valid(new Bundle{
+    val addr = UInt(16.W)
+    val dataw = UInt(8.W)
+    val isWRn = Bool()
+  })
+
+  val resp = Valid(new Bundle{
+    datar = UInt(8.W)
+  })
+}
 
 
 abstract class InterfaceBase extends Module{
@@ -57,11 +133,9 @@ abstract class InterfaceBase extends Module{
 
 
 
-  // val RAMSize: UInt
-  // val MMUNum: UInt
 
-  // val nodeSeqAddr = Reg(UInt(16.W))
-  // val nodeSetAddr = Reg(UInt(16.W))
+
+
 
   // val softReset = Reg(Bool())
   // val logicAddr = Reg(UInt(30.W))
diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala
index d068615..be4d8b7 100644
--- a/src/main/scala/backBoard/shin/SMUnit.scala
+++ b/src/main/scala/backBoard/shin/SMUnit.scala
@@ -61,31 +61,29 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
   }
 
   for( i <- 0 until depth ){
-    io.sram(i).addrw := 0.U
-    io.sram(i).dataw := 0.U
-    io.sram(i).enw   := false.B
+    io.sram(i).wr.addrw := 0.U
+    io.sram(i).wr.dataw := 0.U
+    io.sram(i).wr.enw   := false.B
 
-    io.sram(i).addrr := 0.U
-    io.sram(i).enr   := false.B
+    io.sram(i).rd.addrr := 0.U
+    io.sram(i).rd.enr   := false.B
   }
 
   for( i <- 0 until depth ){
     when( wPtr === i.U & ~isFull ){
-      io.sram(i).addrw := io.sram_w.addrw
-      io.sram(i).dataw := io.sram_w.dataw
-      io.sram(i).enw   := io.sram_w.enw
+      io.sram(i).wr <> io.sram_w.addrw
     }
 
     when( rPtr === i.U & ~isEmpty){
-      io.sram(i).addrr := io.sram_r.addrr
-      io.sram(i).enr   := io.sram_r.enr
+      io.sram(i).rd.addrr := io.sram_r.addrr
+      io.sram(i).rd.enr   := io.sram_r.enr
     }
   }
 
 
 
   io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
-    ( rPtr === i.U ) -> io.sram(i).datar,
+    ( rPtr === i.U ) -> io.sram(i).rd.datar
   })
 
 
diff --git a/src/main/scala/backBoard/shin/SRAMFifo.scala b/src/main/scala/backBoard/shin/SRAMFifo.scala
index 19f15a4..b8c5b33 100644
--- a/src/main/scala/backBoard/shin/SRAMFifo.scala
+++ b/src/main/scala/backBoard/shin/SRAMFifo.scala
@@ -4,62 +4,57 @@ import chisel3._
 import chisel3.util._
 
 class SRAM2kWRIO extends Bundle {
-  val addrw = Output(UInt(11.W))
-  val dataw = Output( UInt(8.W) )
-  val enw   = Output(Bool())
+  val addrw = Input(UInt(11.W))
+  val dataw = Input( UInt(8.W) )
+  val enw   = Input(Bool())
 }
 
 class SRAM2kRDIO extends Bundle {
-  val addrr = Output(UInt(11.W))
-  val datar = Input( UInt(8.W) )
-  val enr   = Output(Bool())
+  val addrr = Input(UInt(11.W))
+  val datar = Output( UInt(8.W) )
+  val enr   = Input(Bool())
 }
 
 
 class SRAM2kIO extends Bundle {
-  val addrr  = Output(UInt(11.W))
-  val addrw  = Output(UInt(11.W))
-
-  val dataw = Output( UInt(8.W) )
-  val datar = Input( UInt(8.W) )
-  val enw   = Output(Bool())
-  val enr   = Output(Bool())
+  val rd = new SRAM2kRDIO
+  val wr = new SRAM2kWRIO
 }
 
-class SRAM2kFifoIO extends Bundle {
-  val sram = new SRAM2kIO
+// class SRAM2kFifoIO extends Bundle {
+//   val sram = new SRAM2kIO
 
-  val enq = Flipped(Decoupled(UInt(8.W)))
-  val deq = Decoupled(UInt(8.W))
-}
+//   val enq = Flipped(Decoupled(UInt(8.W)))
+//   val deq = Decoupled(UInt(8.W))
+// }
 
-class SRAM2kFifo extends Module {
-  val io: SRAM2kFifoIO = IO(new SRAM2kFifoIO)
+// class SRAM2kFifo extends Module {
+//   val io: SRAM2kFifoIO = IO(new SRAM2kFifoIO)
 
-  val wptr = RegInit(0.U((11+1).W))
-  val rptr = RegInit(0.U((11+1).W))
+//   val wptr = RegInit(0.U((11+1).W))
+//   val rptr = RegInit(0.U((11+1).W))
 
-  val isFull  = (wptr.extract(11) =/= rptr.extract(11)) & (wptr(10,0) === rptr(10,0))
-  val isEmpty = (wptr === rptr)
+//   val isFull  = (wptr.extract(11) =/= rptr.extract(11)) & (wptr(10,0) === rptr(10,0))
+//   val isEmpty = (wptr === rptr)
 
 
-  io.sram.addrr := rptr(10,0)
-  io.sram.addrw := wptr(10,0)
+//   io.sram.addrr := rptr(10,0)
+//   io.sram.addrw := wptr(10,0)
 
-  io.sram.dataw := io.enq.bits
-  io.deq.bits := io.sram.datar
-  io.sram.enw   := io.enq.fire
-  io.sram.enr   := true.B
+//   io.sram.dataw := io.enq.bits
+//   io.deq.bits := io.sram.datar
+//   io.sram.enw   := io.enq.fire
+//   io.sram.enr   := true.B
 
-  io.enq.ready := ~isFull
-  io.deq.valid := ~isEmpty
+//   io.enq.ready := ~isFull
+//   io.deq.valid := ~isEmpty
 
-  when( io.enq.fire ){
-    wptr := wptr + 1.U
-  }
+//   when( io.enq.fire ){
+//     wptr := wptr + 1.U
+//   }
 
-  when( io.deq.fire ){
-    rptr := rptr + 1.U
-  }
+//   when( io.deq.fire ){
+//     rptr := rptr + 1.U
+//   }
 
-}
+// }
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index e2ec179..ce9d7e1 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -1,54 +1,108 @@
-// package BACK
+package BACK
 
-// import chisel3._
-// import chisel3.util._
+import chisel3._
+import chisel3.util._
 
 
-// class ShinTopIO extends Bundle{
-// 	val clk8x = Input(Bool())
-// 	val modeSel = Input(Bool())\
+class ShinTopIO extends Bundle{
+  // val clk8x = Input(Bool())
+  // val modeSel = Input(Bool())
 	
-//   val dDatIn   = Input(Bool())
-//   val dDatOut  = Output(Bool())
-//   val uDatIn   = Input(Bool())
-//   val uDatOut  = Output(Bool())
+  // val dDatIn   = Input(Bool())
+  // val dDatOut  = Output(Bool())
+  // val uDatIn   = Input(Bool())
+  // val uDatOut  = Output(Bool())
 
-// 	val qspi = 
-// 	val interrupt = Output(Bool())
-// 	val ctrl      = Input(UInt(4.W))
-// }
+  val downIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
+  val downOut = Decoupled(new AXIS_Bundle(8))
+
+  val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
+  val upOut = Decoupled(new AXIS_Bundle(8))
+
+	// val qspi = 
+	// val interrupt = Output(Bool())
+	// val ctrl      = Input(UInt(4.W))
+
+  val timeStamp = Input(UInt(64.W))
+
+  val sram = MixedVec(
+     Vec(4, new SRAM2kIO)
+     Vec(4, new SRAM2kIO)
+     Vec(4, new SRAM2kIO)
+     Vec(4, new SRAM2kIO)
+     Vec(2, new SRAM2kIO)
+     Vec(2, new SRAM2kIO)
+     Vec(2, new SRAM2kIO)
+     Vec(2, new SRAM2kIO)
+  )
+}
 
 
 
-// class ShinTop extends Module{
-//   val io: ShinTopIO = IO(new ShinTopIO)
+class ShinTop extends Module{
+  val io: ShinTopIO = IO(new ShinTopIO)
 
-//   val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
-// 	val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
+  // val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
+	// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
 
-// 	val slaveParser  = Module(new SlaveParser )
-// 	val masterParser = Module(new MasterParser)
-
-// 	val sram = Module(new ShareSRAMDP)
-
-// 	val interface = Module(new Interface)
+	val slaveParser  = Module(new SlaveParser )
+	val masterParser = Module(new MasterParser)
 
 
-//   sram.io.addrA   := Input(UInt(15.W))
-//   sram.io.datawA  := Input( UInt(8.W) )
-//   sram.io.datarA  := Output( UInt(8.W) )
-//   sram.io.enwA    := Input(Bool())
-//   sram.io.enrA    := Input(Bool())
-//   sram.io.clockA  := Input(Bool())
+  val smUnit = Seq(
+    Module( new SMUnit(depth = 4) )
+    Module( new SMUnit(depth = 4) )
+    Module( new SMUnit(depth = 4) )
+    Module( new SMUnit(depth = 4) )
+    Module( new SMUnit(depth = 2) )
+    Module( new SMUnit(depth = 2) )
+    Module( new SMUnit(depth = 2) )
+    Module( new SMUnit(depth = 2) )
+  )
 
-//   sram.io.addrB  := Input(UInt(15.W))
-//   sram.io.datawB := Input( UInt(8.W) )
-//   sram.io.datarB := Output( UInt(8.W) )
-//   sram.io.enwB   := Input(Bool())
-//   sram.io.enrB   := Input(Bool())
-//   sram.io.clockB := Input(Bool())
+
+  smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
+  smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
+  smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
+  smUnit(6).io.sram_w := slaveParser.io.sram_w(3)
+
+  smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
+  smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
+  smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
+  smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
+
+  smUnit(0).io.enq := slaveParser.io.dSMenq(0)
+  smUnit(2).io.enq := slaveParser.io.dSMenq(1)
+  smUnit(4).io.enq := slaveParser.io.dSMenq(2)
+  smUnit(6).io.enq := slaveParser.io.dSMenq(3)
+
+  smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
+  smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
+  smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
+  smUnit(7).io.deq := slaveParser.io.uSMdeq(3)
+
+  smUnit(0).io.sram <> io.sram(0)
+  smUnit(1).io.sram <> io.sram(1)
+  smUnit(2).io.sram <> io.sram(2)
+  smUnit(3).io.sram <> io.sram(3)
+  smUnit(4).io.sram <> io.sram(4)
+  smUnit(5).io.sram <> io.sram(5)
+  smUnit(6).io.sram <> io.sram(6)
+  smUnit(7).io.sram <> io.sram(7)
+
+
+  slaveParser.io.downIn  <> io.downIn
+  slaveParser.io.downOut <> io.downOut
+  slaveParser.io.upIn    <> io.upIn
+  slaveParser.io.upOut   <> io.upOut
+
+  slaveParser.io.timeStamp := io.timeStamp
 
 
 
 
-// }
+
+
+
+
+}
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index 2769021..d2d3b1e 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -38,17 +38,13 @@ class SlaveParserIO extends Bundle{
   val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
   val upOut = Decoupled(new AXIS_Bundle(8))
 
-  // val sram_r = Flipped(new ShareSRAMIO)
-  // val sram_w = Flipped(new ShareSRAMIO)
+  val sram_w = Vec( 4, Flipped(new SRAM2kWRIO))
+  val sram_r = Vec( 4, Flipped(new SRAM2kRDIO))
 
-  // val dSMenq = Vec(4, Decoupled(UInt(8.W)))
-  // val uSMdeq = Vec(4, Flipped(Decoupled(UInt(8.W))))
+  val dSMenq = Output( Vec(4, Bool()) )
+  val uSMdeq = Output( Vec(4, Bool()) )
 
-  val sram_w = Vec( 4, Flipped(new SRAM2kWRIO) )
-  val sram_r = Vec( 4, Flipped(new SRAM2kRDIO) )
-
-  val dSMenq = Input( Vec(4, Bool()) )
-  val uSMdeq = Input( Vec(4, Bool()) )
+  val trigAddr = Input( Vec(8, UInt(15.W)) )
 
   val timeStamp = Input(UInt(64.W))
 }
@@ -407,29 +403,41 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     }
   }
 
-  val isWrite := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
-    ( ~isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
-    (  isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
+  val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
+    ( ~isDownRecPing & (downSubMsgInfo(0).devIndex === localDevIndex) & ( (downSubMsgInfo(0).operator === 1.U) | (downSubMsgInfo(0).operator === 3.U) )) |
+    (  isDownRecPing & (downSubMsgInfo(1).devIndex === localDevIndex) & ( (downSubMsgInfo(1).operator === 1.U) | (downSubMsgInfo(1).operator === 3.U) ))
   )
 
 
-    val isTermSM = Seq[Bool]
 
-    io.sram_w(0).enw   := isWrite & isWRSM0
-    io.sram_w(0).addrw := addrw(10,0)
-    io.sram_w(0).dataw := downRecParser.io.data.bits
+  io.sram_w(0).enw   := isWrite & isWRSM0
+  io.sram_w(0).addrw := addrw(10,0)
+  io.sram_w(0).dataw := downRecParser.io.data.bits
 
-    io.sram_w(1).enw   := isWrite & isWRSM2
-    io.sram_w(1).addrw := addrw(10,0)
-    io.sram_w(1).dataw := downRecParser.io.data.bits
+  io.sram_w(1).enw   := isWrite & isWRSM2
+  io.sram_w(1).addrw := addrw(10,0)
+  io.sram_w(1).dataw := downRecParser.io.data.bits
+
+  io.sram_w(2).enw   := isWrite & isWRSM4
+  io.sram_w(2).addrw := addrw(10,0)
+  io.sram_w(2).dataw := downRecParser.io.data.bits
+
+  io.sram_w(3).enw   := isWrite & isWRSM6
+  io.sram_w(3).addrw := addrw(10,0)
+  io.sram_w(3).dataw := downRecParser.io.data.bits
+
+
+  
+  io.dSMenq(0) := isWrite & isWRSM0 & io.trigAddr(0) === addrw(10,0)
+  io.uSMdeq(1) := isRead  & isRDSM1 & io.trigAddr(1) === readSMAddr(10,0)
+  io.dSMenq(2) := isWrite & isWRSM2 & io.trigAddr(2) === addrw(10,0)
+  io.uSMdeq(3) := isRead  & isRDSM3 & io.trigAddr(3) === readSMAddr(10,0)
+  io.dSMenq(4) := isWrite & isWRSM4 & io.trigAddr(4) === addrw(10,0)
+  io.uSMdeq(5) := isRead  & isRDSM5 & io.trigAddr(5) === readSMAddr(10,0)
+  io.dSMenq(6) := isWrite & isWRSM6 & io.trigAddr(6) === addrw(10,0)
+  io.uSMdeq(7) := isRead  & isRDSM7 & io.trigAddr(7) === readSMAddr(10,0)
 
-    io.sram_w(2).enw   := isWrite & isWRSM4
-    io.sram_w(2).addrw := addrw(10,0)
-    io.sram_w(2).dataw := downRecParser.io.data.bits
 
-    io.sram_w(3).enw   := isWrite & isWRSM6
-    io.sram_w(3).addrw := addrw(10,0)
-    io.sram_w(3).dataw := downRecParser.io.data.bits
 
 
   //上行接收
@@ -458,7 +466,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     ((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 2.U | upRecParser.io.subMsgReq.bits.operator === 3.U))
 
   val addrr = Reg(UInt(15.W))  
-  val readSMAddr := Mux1H(Seq(
+  val readSMAddr = Mux1H(Seq(
     ( upRecParser.io.stateCurr === STATE_PAYLOAD_WORKCNT ) -> upRecParser.io.subMsgReq.bits.address,
     ( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA    ) -> addrr,
   ))
@@ -474,7 +482,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   }
 
   val upStreamData = Mux1H(Seq(
-    isRDRegister -> ,
+    isRDRegister -> 0.U,
     isRDSM1      -> io.sram_r(0).datar,
     isRDSM3      -> io.sram_r(1).datar,
     isRDSM5      -> io.sram_r(2).datar,
@@ -516,7 +524,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
 trait SlaveParserSync{ this: SlaveParserBase =>
   val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器 
-  val upTimeStamp   = Reg(UInt(64.W)) //下行本地时间戳寄存器
+  val upTimeStamp   = Reg(UInt(64.W)) //上行本地时间戳寄存器
   val mstTimeStamp  = Reg(UInt(64.W)) //主站时间戳
   val mstDeltaTimeStamp = Reg(UInt(32.W)) //主站时间戳差值
   val slvDeltaTimeStamp = Reg(UInt(32.W)) //从站时间戳差值
@@ -546,7 +554,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
   }
 
   //下行接收
-  val isSync := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
+  val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
     ( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === "he".U ) |
     (  isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === "he".U )
   )
@@ -675,36 +683,3 @@ with SlaveParserProbe
 
 
 
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-}
-
-
-
-
-
-class SlaveParser extends SlaveParserBase{
-
-}
diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala
index 8a78480..eb24f89 100644
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -97,8 +97,14 @@ object testModule extends App {
 }
 
 object testShinModule extends App {
+  // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq(
+  //     ChiselGeneratorAnnotation(() => { new SlaveParser }),
+  //   ))
+
   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => { new SlaveParser }),
+      ChiselGeneratorAnnotation(() => { new ShinTopIO }),
     ))
+
+
 }