101 lines
1.9 KiB
Scala
101 lines
1.9 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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// class SRAM2kWRIO extends Bundle {
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// val addrw = Output(UInt(11.W))
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// val dataw = Output( UInt(8.W) )
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// val enw = Output(Bool())
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// }
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// class SRAM2kRDIO extends Bundle {
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// val addrr = Output(UInt(11.W))
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// val datar = Input( UInt(8.W) )
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// val enr = Output(Bool())
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// }
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// class SRAM2kIO extends Bundle {
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// val addrr = Output(UInt(11.W))
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// val addrw = Output(UInt(11.W))
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// val dataw = Output( UInt(8.W) )
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// val datar = Input( UInt(8.W) )
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// val enw = Output(Bool())
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// val enr = Output(Bool())
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// }
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class SMUnitIO(depth: Int) extends Bundle {
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val sram_w = Flipped(new SRAM2kWRIO)
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val sram_r = Flipped(new SRAM2kRDIO)
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val enq = Input(Bool())
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val deq = Input(Bool())
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val sram = Vec(depth, new SRAM2kIO)
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}
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abstract class SMUnitBase(depth: Int = 4) extends Module {
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val io: SMUnitIO = IO(new SMUnitIO(depth))
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val wPtr = RegInit(0.U((log2Ceil(depth)+1).W))
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val rPtr = RegInit(0.U((log2Ceil(depth)+1).W))
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val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth))
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// ( wPtr.extract(2) =/= rPtr.extract(2) ) & ( wPtr(1,0) === rPtr(1,0) )
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val isEmpty = ( wPtr === rPtr )
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when( io.enq ){
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wPtr := wPtr + 1.U
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}
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when( io.deq ){
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rPtr := rPtr + 1.U
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}
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for( i <- 0 until depth ){
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io.sram(i).wr.addrw := 0.U
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io.sram(i).wr.dataw := 0.U
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io.sram(i).wr.enw := false.B
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io.sram(i).rd.addrr := 0.U
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io.sram(i).rd.enr := false.B
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}
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for( i <- 0 until depth ){
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when( wPtr === i.U & ~isFull ){
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io.sram(i).wr <> io.sram_w.addrw
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}
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when( rPtr === i.U & ~isEmpty){
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io.sram(i).rd.addrr := io.sram_r.addrr
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io.sram(i).rd.enr := io.sram_r.enr
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}
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}
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io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
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( rPtr === i.U ) -> io.sram(i).rd.datar
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})
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}
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class SMUnit(depth: Int = 4) extends SMUnitBase(depth) {
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}
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