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修复:SM fifo切换错误

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This commit is contained in:
Ruige Lee
2025-05-16 15:39:48 +08:00
parent 23fdd91ba3
commit 3f1fdc725a
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/backBoard/shin/SMUnit.scala
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@@ -66,11 +66,11 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
} }
for( i <- 0 until depth ){ for( i <- 0 until depth ){
when( wPtr === i.U & ~isFull ){ when( (wPtr(log2Ceil(depth)-1, 0)) === i.U & ~isFull ){
io.sram(i).wr <> io.sram_w io.sram(i).wr <> io.sram_w
} }
when( rPtr === i.U & ~isEmpty){ when( (rPtr(log2Ceil(depth)-1, 0)) === i.U & ~isEmpty){
io.sram(i).rd.addrr := io.sram_r.addrr io.sram(i).rd.addrr := io.sram_r.addrr
io.sram(i).rd.enr := io.sram_r.enr io.sram(i).rd.enr := io.sram_r.enr
} }
@@ -79,7 +79,7 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
io.sram_r.datar := Mux1H( ( 0 until depth).map{ i => io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
( rPtr === i.U ) -> io.sram(i).rd.datar ( (rPtr(log2Ceil(depth)-1, 0)) === i.U ) -> io.sram(i).rd.datar
}) })