From 3f1fdc725ade74c65a223beabaa15fb6d61da52f Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 16 May 2025 15:39:48 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8D:SM=20fifo=E5=88=87=E6=8D=A2?= =?UTF-8?q?=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SMUnit.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala index 12b61f8..b0a407e 100644 --- a/src/main/scala/backBoard/shin/SMUnit.scala +++ b/src/main/scala/backBoard/shin/SMUnit.scala @@ -66,11 +66,11 @@ abstract class SMUnitBase(depth: Int = 4) extends Module { } for( i <- 0 until depth ){ - when( wPtr === i.U & ~isFull ){ + when( (wPtr(log2Ceil(depth)-1, 0)) === i.U & ~isFull ){ io.sram(i).wr <> io.sram_w } - when( rPtr === i.U & ~isEmpty){ + when( (rPtr(log2Ceil(depth)-1, 0)) === i.U & ~isEmpty){ io.sram(i).rd.addrr := io.sram_r.addrr io.sram(i).rd.enr := io.sram_r.enr } @@ -79,7 +79,7 @@ abstract class SMUnitBase(depth: Int = 4) extends Module { io.sram_r.datar := Mux1H( ( 0 until depth).map{ i => - ( rPtr === i.U ) -> io.sram(i).rd.datar + ( (rPtr(log2Ceil(depth)-1, 0)) === i.U ) -> io.sram(i).rd.datar })