diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala
index 12b61f8..b0a407e 100644
--- a/src/main/scala/backBoard/shin/SMUnit.scala
+++ b/src/main/scala/backBoard/shin/SMUnit.scala
@@ -66,11 +66,11 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
   }
 
   for( i <- 0 until depth ){
-    when( wPtr === i.U & ~isFull ){
+    when( (wPtr(log2Ceil(depth)-1, 0)) === i.U & ~isFull ){
       io.sram(i).wr <> io.sram_w
     }
 
-    when( rPtr === i.U & ~isEmpty){
+    when( (rPtr(log2Ceil(depth)-1, 0)) === i.U & ~isEmpty){
       io.sram(i).rd.addrr := io.sram_r.addrr
       io.sram(i).rd.enr   := io.sram_r.enr
     }
@@ -79,7 +79,7 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
 
 
   io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
-    ( rPtr === i.U ) -> io.sram(i).rd.datar
+    ( (rPtr(log2Ceil(depth)-1, 0)) === i.U ) -> io.sram(i).rd.datar
   })