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4倍频采3次

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RuigeLee
2024-09-20 14:55:43 +08:00
parent 1368e9037d
commit 3c357b54e0
2 changed files with 19 additions and 8 deletions
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4
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -23,8 +23,8 @@ abstract class CDRInBase extends Module{
}
trait CDRInOverSample{ this: CDRInBase =>
val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
val arbResult = VecInit(sampleReg).count( (x:Bool) => (x === true.B) ) > (sampleRate / 2).U
val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate-1 ) }
val arbResult = VecInit(sampleReg).count( (x:Bool) => (x === true.B) ) > ((sampleRate-1) / 2).U
val syncSerDat = ShiftRegister( arbResult, 2 )
}