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优先级mux引入了额外的一拍数据

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RuigeLee
2024-11-12 15:55:20 +08:00
parent 9e0d0a4177
commit 392ebf902c
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -41,7 +41,7 @@ trait CDRInOverSample{ this: CDRInBase =>
} }
val syncSerDat = ShiftRegister( val syncSerDat = ShiftRegister(
PriorityMux( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } ) Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
, 2 ) , 2 )
} }

2
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -77,7 +77,7 @@ class CDROut extends Module{
} .elsewhen( stateCurr === STATE_PAYLOAD ){ } .elsewhen( stateCurr === STATE_PAYLOAD ){
shiftData := io.axis.bits.tdata shiftData := io.axis.bits.tdata
} .elsewhen( stateCurr === STATE_FCS ){ } .elsewhen( stateCurr === STATE_FCS ){
shiftData := PriorityMux(Seq( shiftData := Mux1H(Seq(
( byteCnt === 0.U) -> ~crcOut( 7,0), ( byteCnt === 0.U) -> ~crcOut( 7,0),
( byteCnt === 1.U) -> ~crcOut(15,8), ( byteCnt === 1.U) -> ~crcOut(15,8),
( byteCnt === 2.U) -> ~crcOut(23,16), ( byteCnt === 2.U) -> ~crcOut(23,16),