From 392ebf902cd34c98b8190fc7a0201235836dedd4 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 12 Nov 2024 15:55:20 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BC=98=E5=85=88=E7=BA=A7mux=E5=BC=95?= =?UTF-8?q?=E5=85=A5=E4=BA=86=E9=A2=9D=E5=A4=96=E7=9A=84=E4=B8=80=E6=8B=8D?= =?UTF-8?q?=E6=95=B0=E6=8D=AE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 2 +- src/main/scala/backBoard/ebus/CDROut.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 762f09d..c1c5359 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -41,7 +41,7 @@ trait CDRInOverSample{ this: CDRInBase => } val syncSerDat = ShiftRegister( - PriorityMux( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } ) + Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } ) , 2 ) } diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala index 553004e..9000be4 100644 --- a/src/main/scala/backBoard/ebus/CDROut.scala +++ b/src/main/scala/backBoard/ebus/CDROut.scala @@ -77,7 +77,7 @@ class CDROut extends Module{ } .elsewhen( stateCurr === STATE_PAYLOAD ){ shiftData := io.axis.bits.tdata } .elsewhen( stateCurr === STATE_FCS ){ - shiftData := PriorityMux(Seq( + shiftData := Mux1H(Seq( ( byteCnt === 0.U) -> ~crcOut( 7,0), ( byteCnt === 1.U) -> ~crcOut(15,8), ( byteCnt === 2.U) -> ~crcOut(23,16),