diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 762f09d..c1c5359 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -41,7 +41,7 @@ trait CDRInOverSample{ this: CDRInBase =>
   }
 
   val syncSerDat = ShiftRegister( 
-    PriorityMux( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
+    Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
     , 2 )
 }
 
diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala
index 553004e..9000be4 100644
--- a/src/main/scala/backBoard/ebus/CDROut.scala
+++ b/src/main/scala/backBoard/ebus/CDROut.scala
@@ -77,7 +77,7 @@ class CDROut extends Module{
       } .elsewhen( stateCurr === STATE_PAYLOAD ){
         shiftData := io.axis.bits.tdata
       } .elsewhen( stateCurr === STATE_FCS ){
-        shiftData := PriorityMux(Seq(
+        shiftData := Mux1H(Seq(
           ( byteCnt === 0.U) -> ~crcOut( 7,0),
           ( byteCnt === 1.U) -> ~crcOut(15,8),
           ( byteCnt === 2.U) -> ~crcOut(23,16),