优先级mux引入了额外的一拍数据

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -41,7 +41,7 @@ trait CDRInOverSample{ this: CDRInBase =>
   }
 
   val syncSerDat = ShiftRegister( 
-    PriorityMux( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
+    Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
     , 2 )
 }