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fix sram

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Ruige Lee (WSL)
2023-08-21 14:52:21 +08:00
parent 5f15e94ae3
commit 37ac7817d7
1 changed files with 1 additions and 2 deletions
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3
src/main/scala/backBoard/MirrorSRAM.scala
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@@ -47,7 +47,7 @@ class MirrorSRAM extends BlackBox with HasBlackBoxInline {
val io: MirrorSRAMIO = IO(new MirrorSRAMIO) val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
setInline("lvds_bus_master.v", setInline("microSRAM.v",
""" """
| module MirrorSRAM( | module MirrorSRAM(
| output [7:0] datar, | output [7:0] datar,
@@ -86,7 +86,6 @@ class MirrorSRAM extends BlackBox with HasBlackBoxInline {
| defparam bram_sdpb_0.BIT_WIDTH_1 = 8; | defparam bram_sdpb_0.BIT_WIDTH_1 = 8;
| defparam bram_sdpb_0.RESET_MODE = "SYNC"; | defparam bram_sdpb_0.RESET_MODE = "SYNC";
| |
| );
|endmodule |endmodule
""".stripMargin) """.stripMargin)
} }