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没有片选时，AD必须为高阻态

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RuigeLee
2024-03-16 20:45:12 +08:00
parent ca60205abc
commit 2b18de45e6
1 changed files with 1 additions and 1 deletions
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src/main/scala/backBoard/BackBoardMst.scala
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@@ -125,7 +125,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B ) val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B )
val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B ) val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )
io.FSMC.ADOEn := fsmcRDSync(1) io.FSMC.ADOEn := fsmcRDSync(1) & fsmcCSSync(1) & ~fsmcADVSync(1)
val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVSync(2) & fsmcADVSync(1) ) val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVSync(2) & fsmcADVSync(1) )