diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 0d50ec1..0e02ca8 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -125,7 +125,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     val fsmcWRSync  = ShiftRegisters( ~io.FSMC.wrn,  3, false.B, true.B )
     val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )  
 
-    io.FSMC.ADOEn := fsmcRDSync(1)
+    io.FSMC.ADOEn := fsmcRDSync(1) & fsmcCSSync(1) & ~fsmcADVSync(1)
 
     val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVSync(2) & fsmcADVSync(1) )