From 2b18de45e6b5ce8d250cdb52c78c368c78b7840a Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Sat, 16 Mar 2024 20:45:12 +0800 Subject: [PATCH] =?UTF-8?q?=E6=B2=A1=E6=9C=89=E7=89=87=E9=80=89=E6=97=B6?= =?UTF-8?q?=EF=BC=8CAD=E5=BF=85=E9=A1=BB=E4=B8=BA=E9=AB=98=E9=98=BB?= =?UTF-8?q?=E6=80=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/BackBoardMst.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala index 0d50ec1..0e02ca8 100644 --- a/src/main/scala/backBoard/BackBoardMst.scala +++ b/src/main/scala/backBoard/BackBoardMst.scala @@ -125,7 +125,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase => val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B ) val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B ) - io.FSMC.ADOEn := fsmcRDSync(1) + io.FSMC.ADOEn := fsmcRDSync(1) & fsmcCSSync(1) & ~fsmcADVSync(1) val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVSync(2) & fsmcADVSync(1) )