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取消3个寄存器只能配置一次的特性

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RuigeLee
2025-09-11 11:28:05 +08:00
parent f0e5895505
commit 2969cf70a1
1 changed files with 3 additions and 4 deletions
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7
src/main/scala/backBoard/shin/Interface.scala
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@@ -630,12 +630,11 @@ trait InterfaceMCUop{ this: InterfaceBase =>
cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U(2.W), isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U ) cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U(2.W), isEnW & addrw === "h0".U )
cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U ) cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U )
cReg.spiSel := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U ) cReg.spiSel := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U )
mReg.txSM := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U ) mReg.txSM := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U )
mReg.rxSM := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U ) mReg.rxSM := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )