From 2969cf70a1072e36866259c016d23341af7e4208 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 11 Sep 2025 11:28:05 +0800 Subject: [PATCH] =?UTF-8?q?=E5=8F=96=E6=B6=883=E4=B8=AA=E5=AF=84=E5=AD=98?= =?UTF-8?q?=E5=99=A8=E5=8F=AA=E8=83=BD=E9=85=8D=E7=BD=AE=E4=B8=80=E6=AC=A1?= =?UTF-8?q?=E7=9A=84=E7=89=B9=E6=80=A7?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 51e3e26..bd51d81 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -630,12 +630,11 @@ trait InterfaceMCUop{ this: InterfaceBase => - cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U(2.W), isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U ) + cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U(2.W), isEnW & addrw === "h0".U ) - cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U ) - cReg.spiSel := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U ) - + cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U ) + cReg.spiSel := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U ) mReg.txSM := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U ) mReg.rxSM := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )