diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 51e3e26..bd51d81 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -630,12 +630,11 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
 
 
-  cReg.mstOrSlv  := RegEnable( dataw(1,0), 0.U(2.W), isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U )
+  cReg.mstOrSlv  := RegEnable( dataw(1,0), 0.U(2.W), isEnW & addrw === "h0".U )
 
   
-  cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
-  cReg.spiSel  := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
-
+  cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U )
+  cReg.spiSel  := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U )
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )