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clean up

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RuigeLee
2023-10-25 16:04:53 +08:00
parent 6e25f934b2
commit 1e6f2df9ae
4 changed files with 2 additions and 8 deletions
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5
src/main/scala/Switch/MacRegisters.scala
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@@ -37,7 +37,6 @@ class Mac_Config_Bundle extends Bundle{
val r_ExDfrEn = Output(Bool()) val r_ExDfrEn = Output(Bool())
val r_LoopBck = Output(Bool()) val r_LoopBck = Output(Bool())
val r_IFG = Output(Bool()) val r_IFG = Output(Bool())
val r_Iam = Output(Bool())
val r_NoPre = Output(Bool()) val r_NoPre = Output(Bool())
val r_TxEn = Output(Bool()) val r_TxEn = Output(Bool())
val r_RxEn = Output(Bool()) val r_RxEn = Output(Bool())
@@ -114,7 +113,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
val ExDfrEn = RegInit(false.B) val ExDfrEn = RegInit(false.B)
val LoopBck = RegInit(false.B) val LoopBck = RegInit(false.B)
val IFG = RegInit(false.B) val IFG = RegInit(false.B)
val Iam = RegInit(false.B)
val NoPre = RegInit(false.B) val NoPre = RegInit(false.B)
val TxEn = RegInit(false.B) val TxEn = RegInit(false.B)
val RxEn = RegInit(false.B) val RxEn = RegInit(false.B)
@@ -196,7 +194,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
RegField(1, TxEn , RegFieldDesc( "TxEn", "TxEn", reset = Some(0) ) ), RegField(1, TxEn , RegFieldDesc( "TxEn", "TxEn", reset = Some(0) ) ),
RegField(1, NoPre , RegFieldDesc( "NoPre", "NoPre", reset = Some(0) ) ), RegField(1, NoPre , RegFieldDesc( "NoPre", "NoPre", reset = Some(0) ) ),
RegField.r(1, 0.U , RegFieldDesc( "Bro", "Bro", reset = Some(0) ) ), RegField.r(1, 0.U , RegFieldDesc( "Bro", "Bro", reset = Some(0) ) ),
RegField(1, Iam , RegFieldDesc( "Iam", "Iam", reset = Some(0) ) ), RegField.r(1, 0.U , RegFieldDesc( "Iam", "Iam Unused", reset = Some(0) ) ),
RegField.r(1, 0.U , RegFieldDesc( "Pro", "Pro", reset = Some(0) ) ), RegField.r(1, 0.U , RegFieldDesc( "Pro", "Pro", reset = Some(0) ) ),
RegField(1, IFG , RegFieldDesc( "IFG", "IFG", reset = Some(0) ) ), RegField(1, IFG , RegFieldDesc( "IFG", "IFG", reset = Some(0) ) ),
RegField(1, LoopBck, RegFieldDesc( "LoopBck", "LoopBck", reset = Some(0) ) ), RegField(1, LoopBck, RegFieldDesc( "LoopBck", "LoopBck", reset = Some(0) ) ),
@@ -362,7 +360,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
io.r_ExDfrEn := ExDfrEn io.r_ExDfrEn := ExDfrEn
io.r_LoopBck := LoopBck io.r_LoopBck := LoopBck
io.r_IFG := IFG io.r_IFG := IFG
io.r_Iam := Iam
io.r_NoPre := NoPre io.r_NoPre := NoPre
io.r_TxEn := TxEn & (TX_BD_NUM > 0.U) // Transmission is enabled when there is at least one TxBD. io.r_TxEn := TxEn & (TX_BD_NUM > 0.U) // Transmission is enabled when there is at least one TxBD.
io.r_RxEn := RxEn & (TX_BD_NUM < "h80".U) // Reception is enabled when there is at least one RxBD. io.r_RxEn := RxEn & (TX_BD_NUM < "h80".U) // Reception is enabled when there is at least one RxBD.

1
src/main/scala/Switch/mac/MAC.scala
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@@ -496,7 +496,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
rxethmac.io.MAC := r_MAC rxethmac.io.MAC := r_MAC
rxethmac.io.r_HASH0 := r_HASH0 rxethmac.io.r_HASH0 := r_HASH0
rxethmac.io.r_HASH1 := r_HASH1 rxethmac.io.r_HASH1 := r_HASH1
rxethmac.io.PassAll := true.B
rxethmac.io.ControlFrmAddressOK := ControlFrmAddressOK rxethmac.io.ControlFrmAddressOK := ControlFrmAddressOK
RxData := rxethmac.io.RxData RxData := rxethmac.io.RxData

3
src/main/scala/Switch/mac/MacRx.scala
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@@ -16,7 +16,6 @@ class MacRxIO extends Bundle{
val MAC = Input(UInt(48.W)) // Station Address val MAC = Input(UInt(48.W)) // Station Address
val r_HASH0 = Input(UInt(32.W)) // lower 4 bytes Hash Table val r_HASH0 = Input(UInt(32.W)) // lower 4 bytes Hash Table
val r_HASH1 = Input(UInt(32.W)) // upper 4 bytes Hash Table val r_HASH1 = Input(UInt(32.W)) // upper 4 bytes Hash Table
val PassAll = Input(Bool())
val ControlFrmAddressOK = Input(Bool()) val ControlFrmAddressOK = Input(Bool())
val RxData = Output(UInt(8.W)) val RxData = Output(UInt(8.W))
@@ -206,7 +205,7 @@ trait MacRxFAddrCheck { this: MacRxBase =>
when(ByteCntEq0){ when(ByteCntEq0){
AddressMiss := false.B AddressMiss := false.B
} .elsewhen(ByteCntEq7 & RxCheckEn){ } .elsewhen(ByteCntEq7 & RxCheckEn){
AddressMiss := (~((io.PassAll & io.ControlFrmAddressOK))); AddressMiss := (~((io.ControlFrmAddressOK)));
} }
val IntHash = Mux(CrcHash.extract(5), io.r_HASH1, io.r_HASH0) val IntHash = Mux(CrcHash.extract(5), io.r_HASH1, io.r_HASH0)

1
src/main/scala/Switch/mac/MacTx.scala
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@@ -21,7 +21,6 @@ class MacTxIO extends Bundle{
val IPGR1 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR1 (from register) val IPGR1 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR1 (from register)
val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register) val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register)
val CollValid = Input(UInt(6.W)) // Valid collision window (from register) val CollValid = Input(UInt(6.W)) // Valid collision window (from register)
val MaxRet = Input(UInt(4.W)) // Maximum retry number (from register)
val ExDfrEn = Input(Bool()) // Excessive defferal enable (from register) val ExDfrEn = Input(Bool()) // Excessive defferal enable (from register)
val MTxD = Output(UInt(4.W)) // Transmit nibble (to PHY) val MTxD = Output(UInt(4.W)) // Transmit nibble (to PHY)