From 1e6f2df9aee01f6cc36a75cc300414c451109b72 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 25 Oct 2023 16:04:53 +0800 Subject: [PATCH] clean up --- src/main/scala/Switch/MacRegisters.scala | 5 +---- src/main/scala/Switch/mac/MAC.scala | 1 - src/main/scala/Switch/mac/MacRx.scala | 3 +-- src/main/scala/Switch/mac/MacTx.scala | 1 - 4 files changed, 2 insertions(+), 8 deletions(-) diff --git a/src/main/scala/Switch/MacRegisters.scala b/src/main/scala/Switch/MacRegisters.scala index 9b58f5e..773b1de 100644 --- a/src/main/scala/Switch/MacRegisters.scala +++ b/src/main/scala/Switch/MacRegisters.scala @@ -37,7 +37,6 @@ class Mac_Config_Bundle extends Bundle{ val r_ExDfrEn = Output(Bool()) val r_LoopBck = Output(Bool()) val r_IFG = Output(Bool()) - val r_Iam = Output(Bool()) val r_NoPre = Output(Bool()) val r_TxEn = Output(Bool()) val r_RxEn = Output(Bool()) @@ -114,7 +113,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out val ExDfrEn = RegInit(false.B) val LoopBck = RegInit(false.B) val IFG = RegInit(false.B) - val Iam = RegInit(false.B) val NoPre = RegInit(false.B) val TxEn = RegInit(false.B) val RxEn = RegInit(false.B) @@ -196,7 +194,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out RegField(1, TxEn , RegFieldDesc( "TxEn", "TxEn", reset = Some(0) ) ), RegField(1, NoPre , RegFieldDesc( "NoPre", "NoPre", reset = Some(0) ) ), RegField.r(1, 0.U , RegFieldDesc( "Bro", "Bro", reset = Some(0) ) ), - RegField(1, Iam , RegFieldDesc( "Iam", "Iam", reset = Some(0) ) ), + RegField.r(1, 0.U , RegFieldDesc( "Iam", "Iam Unused", reset = Some(0) ) ), RegField.r(1, 0.U , RegFieldDesc( "Pro", "Pro", reset = Some(0) ) ), RegField(1, IFG , RegFieldDesc( "IFG", "IFG", reset = Some(0) ) ), RegField(1, LoopBck, RegFieldDesc( "LoopBck", "LoopBck", reset = Some(0) ) ), @@ -362,7 +360,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out io.r_ExDfrEn := ExDfrEn io.r_LoopBck := LoopBck io.r_IFG := IFG - io.r_Iam := Iam io.r_NoPre := NoPre io.r_TxEn := TxEn & (TX_BD_NUM > 0.U) // Transmission is enabled when there is at least one TxBD. io.r_RxEn := RxEn & (TX_BD_NUM < "h80".U) // Reception is enabled when there is at least one RxBD. diff --git a/src/main/scala/Switch/mac/MAC.scala b/src/main/scala/Switch/mac/MAC.scala index 3f256e7..ab5955c 100644 --- a/src/main/scala/Switch/mac/MAC.scala +++ b/src/main/scala/Switch/mac/MAC.scala @@ -496,7 +496,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M rxethmac.io.MAC := r_MAC rxethmac.io.r_HASH0 := r_HASH0 rxethmac.io.r_HASH1 := r_HASH1 - rxethmac.io.PassAll := true.B rxethmac.io.ControlFrmAddressOK := ControlFrmAddressOK RxData := rxethmac.io.RxData diff --git a/src/main/scala/Switch/mac/MacRx.scala b/src/main/scala/Switch/mac/MacRx.scala index 4898d25..2ab432d 100644 --- a/src/main/scala/Switch/mac/MacRx.scala +++ b/src/main/scala/Switch/mac/MacRx.scala @@ -16,7 +16,6 @@ class MacRxIO extends Bundle{ val MAC = Input(UInt(48.W)) // Station Address val r_HASH0 = Input(UInt(32.W)) // lower 4 bytes Hash Table val r_HASH1 = Input(UInt(32.W)) // upper 4 bytes Hash Table - val PassAll = Input(Bool()) val ControlFrmAddressOK = Input(Bool()) val RxData = Output(UInt(8.W)) @@ -206,7 +205,7 @@ trait MacRxFAddrCheck { this: MacRxBase => when(ByteCntEq0){ AddressMiss := false.B } .elsewhen(ByteCntEq7 & RxCheckEn){ - AddressMiss := (~((io.PassAll & io.ControlFrmAddressOK))); + AddressMiss := (~((io.ControlFrmAddressOK))); } val IntHash = Mux(CrcHash.extract(5), io.r_HASH1, io.r_HASH0) diff --git a/src/main/scala/Switch/mac/MacTx.scala b/src/main/scala/Switch/mac/MacTx.scala index 98436b0..d5a43d6 100644 --- a/src/main/scala/Switch/mac/MacTx.scala +++ b/src/main/scala/Switch/mac/MacTx.scala @@ -21,7 +21,6 @@ class MacTxIO extends Bundle{ val IPGR1 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR1 (from register) val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register) val CollValid = Input(UInt(6.W)) // Valid collision window (from register) - val MaxRet = Input(UInt(4.W)) // Maximum retry number (from register) val ExDfrEn = Input(Bool()) // Excessive defferal enable (from register) val MTxD = Output(UInt(4.W)) // Transmit nibble (to PHY)