403 lines
14 KiB
Scala
403 lines
14 KiB
Scala
package MAC
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import chisel3._
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import chisel3.util._
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class MacTxIO extends Bundle{
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val TxStartFrm = Input(Bool()) // Transmit packet start frame
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val TxEndFrm = Input(Bool()) // Transmit packet end frame
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val TxData = Input(UInt(8.W)) // Transmit packet data byte
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val CarrierSense = Input(Bool()) // Carrier sense (synchronized)
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val Collision = Input(Bool()) // Collision (synchronized)
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val Pad = Input(Bool()) // Pad enable (from register)
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val CrcEn = Input(Bool()) // Crc enable (from register)
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val FullD = Input(Bool()) // Full duplex (from register)
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val DlyCrcEn = Input(Bool()) // Delayed Crc enabled (from register)
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val MinFL = Input(UInt(16.W)) // Minimum frame length (from register)
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val MaxFL = Input(UInt(16.W)) // Maximum frame length (from register)
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val IPGT = Input(UInt(7.W)) // Back to back transmit inter packet gap parameter (from register)
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val IPGR1 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR1 (from register)
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val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register)
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val CollValid = Input(UInt(6.W)) // Valid collision window (from register)
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val ExDfrEn = Input(Bool()) // Excessive defferal enable (from register)
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val MTxD = Output(UInt(4.W)) // Transmit nibble (to PHY)
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val MTxEn = Output(Bool()) // Transmit enable (to PHY)
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val MTxErr = Output(Bool()) // Transmit error (to PHY)
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val TxDone = Output(Bool()) // Transmit packet done (to RISC)
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val TxAbort = Output(Bool()) // Transmit packet abort (to RISC)
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val TxUsedData = Output(Bool()) // Transmit packet used data (to RISC)
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val WillTransmit = Output(Bool()) // Will transmit (to RxEthMAC)
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val ResetCollision = Output(Bool()) // Reset Collision (for synchronizing collision)
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val StartTxDone = Output(Bool())
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val StartTxAbort = Output(Bool())
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val MaxCollisionOccured= Output(Bool())
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val LateCollision = Output(Bool())
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val DeferIndication = Output(Bool())
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val StatePreamble = Output(Bool())
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val StateData = Output(UInt(2.W))
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}
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abstract class MacTxBase extends Module with RequireAsyncReset{
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val io: MacTxIO = IO(new MacTxIO)
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val StartIPG = Wire(Bool())
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val StartPreamble = Wire(Bool())
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val StartData = Wire( Vec(2,Bool()))
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val StartFCS = Wire(Bool())
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val StartJam = Wire(Bool())
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val StartDefer = Wire(Bool())
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val StateSFD = Wire(Bool())
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val CrcError = Wire(Bool())
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val NibbleMinFl = Wire(Bool())
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val ExcessiveDefer = Wire(Bool())
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val StateIPG = RegInit(false.B)
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val StateIdle = RegInit(false.B)
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val StatePreamble = RegInit(false.B); io.StatePreamble := StatePreamble
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val StateData = RegNext( Cat(StartData(1), StartData(0)), 0.U(2.W)); io.StateData := StateData
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val StatePAD = RegInit(false.B)
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val StateFCS = RegInit(false.B)
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val StateJam = RegInit(false.B)
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val StateJam_q = RegNext(StateJam, false.B)
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val StateDefer = RegInit(true.B)
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val Rule1 = RegInit(false.B)
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val ColWindow = RegInit(true.B)
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val DlyCrcCnt = RegInit(0.U(3.W)) // Delayed CRC counter
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val PacketFinished_q = RegInit(false.B)
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val ByteCnt = RegInit(0.U(16.W)) // Transmit Byte Counter
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val NibCnt = RegInit(0.U(16.W)) // Nibble Counter
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val NibCntEq7 = NibCnt === 7.U
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val NibCntEq15 = NibCnt === 15.U
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}
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trait MacTxFSM { this: MacTxBase =>
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// Defining the next state
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StartIPG := StateDefer & ~ExcessiveDefer & ~io.CarrierSense
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val StartIdle = StateIPG & (Rule1 & NibCnt(6,0) >= io.IPGT | ~Rule1 & NibCnt(6,0) >= io.IPGR2)
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StartPreamble := StateIdle & io.TxStartFrm & ~io.CarrierSense
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StartData(0) := ~io.Collision & (StatePreamble & NibCntEq15 | StateData(1) & ~io.TxEndFrm)
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StartData(1) := ~io.Collision & StateData(0)
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val StartPAD = ~io.Collision & StateData(1) & io.TxEndFrm & io.Pad & ~NibbleMinFl
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StartFCS :=
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(~io.Collision & StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & io.CrcEn) |
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(~io.Collision & StatePAD & NibbleMinFl & io.CrcEn)
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StartJam := (io.Collision ) & ((StatePreamble & NibCntEq15) | (StateData(1) | StateData(0)) | StatePAD | StateFCS)
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StartDefer :=
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(StateIPG & ~Rule1 & io.CarrierSense & NibCnt(6,0) <= io.IPGR1 & NibCnt(6,0) =/= io.IPGR2) |
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(StateIdle & io.CarrierSense) |
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(StateJam & NibCntEq7) |
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io.StartTxDone
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io.DeferIndication := StateIdle & io.CarrierSense
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when(StartDefer | StartIdle){
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StateIPG := false.B
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}.elsewhen(StartIPG){
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StateIPG := true.B
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}
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when(StartDefer | StartPreamble){
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StateIdle := false.B
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}.elsewhen(StartIdle){
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StateIdle := true.B
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}
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when(StartData(0) | StartJam){
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StatePreamble := false.B
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} .elsewhen(StartPreamble){
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StatePreamble := true.B
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}
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when(StartFCS | StartJam){
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StatePAD := false.B
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}.elsewhen(StartPAD){
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StatePAD := true.B
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}
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when(StartJam | StartDefer){
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StateFCS := false.B
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} .elsewhen(StartFCS){
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StateFCS := true.B
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}
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when(StartDefer){
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StateJam := false.B
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} .elsewhen(StartJam){
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StateJam := true.B
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}
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when(StartIPG){
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StateDefer := false.B
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} .elsewhen(StartDefer){
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StateDefer := true.B
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}
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// This sections defines which interpack gap rule to use
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when(StateIdle){
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Rule1 := false.B
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} .elsewhen(StatePreamble | io.FullD){
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Rule1 := true.B
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}
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}
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trait MacTxCounter { this: MacTxBase =>
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val ByteCntMax = Wire(Bool())
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val IncrementNibCnt =
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StateIPG | StatePreamble |
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(StateData(1) | StateData(0)) |
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StatePAD | StateFCS | StateJam |
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(StateDefer & ~ExcessiveDefer & io.TxStartFrm)
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val ResetNibCnt =
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(StateDefer & ExcessiveDefer & ~io.TxStartFrm) |
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(StatePreamble & NibCntEq15) |
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(StateJam & NibCntEq7) |
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StateIdle | StartDefer | StartIPG | StartFCS | StartJam
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when(ResetNibCnt){
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NibCnt := 0.U
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} .elsewhen(IncrementNibCnt){
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NibCnt := NibCnt + 1.U
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}
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NibbleMinFl := NibCnt >= (((io.MinFL-4.U)<<1) - 1.U) // FCS should not be included in NibbleMinFl
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ExcessiveDefer := NibCnt(13,0) === "h17b7".U & ~io.ExDfrEn; // 6071 nibbles
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val IncrementByteCnt =
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(StateData(1) & ~ByteCntMax) |
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((StatePAD | StateFCS) & NibCnt.extract(0) & ~ByteCntMax)
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val ResetByteCnt =
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(StateIdle & io.TxStartFrm) |
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PacketFinished_q
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ByteCntMax := ByteCnt.andR
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when(ResetByteCnt){
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ByteCnt := 0.U
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} .elsewhen(IncrementByteCnt){
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ByteCnt := ByteCnt + 1.U
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}
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when((StateData(1) & DlyCrcCnt === 4.U) | StartJam | PacketFinished_q){
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DlyCrcCnt := 0.U
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}.elsewhen(io.DlyCrcEn & (StateSFD | StateData(1) & (DlyCrcCnt.orR))){
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DlyCrcCnt := DlyCrcCnt + 1.U
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}
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}
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trait MacTxCRC{ this: MacTxBase =>
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val Initialize_Crc = StateIdle | StatePreamble | (DlyCrcCnt.orR)
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val Enable_Crc = ~StateFCS
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val Data_Crc =
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Mux1H(Seq(
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StateData(0) -> Cat( io.TxData(0), io.TxData(1), io.TxData(2), io.TxData(3) ),
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StateData(1) -> Cat( io.TxData(4), io.TxData(5), io.TxData(6), io.TxData(7) ),
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))
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val Crc = RegInit("hFFFFFFFF".U(32.W))
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when( Initialize_Crc ){
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Crc := "hFFFFFFFF".U
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} .otherwise{
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Crc := Cat(
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Crc.extract(27),
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Crc.extract(26),
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(Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(25),
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(Enable_Crc & (Data_Crc.extract(2) ^ Crc.extract(30))) ^ Crc.extract(24),
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(Enable_Crc & (Data_Crc.extract(1) ^ Crc.extract(29))) ^ Crc.extract(23),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(0) ^ Crc.extract(31) ^ Crc.extract(28))) ^ Crc.extract(22),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Crc.extract(31) ^ Crc.extract(30))) ^ Crc.extract(21),
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(Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(30) ^ Crc.extract(29))) ^ Crc.extract(20),
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(Enable_Crc & (Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(29) ^ Crc.extract(28))) ^ Crc.extract(19),
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(Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28))) ^ Crc.extract(18),
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Crc.extract(17),
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Crc.extract(16),
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(Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(15),
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(Enable_Crc & (Data_Crc.extract(2) ^ Crc.extract(30))) ^ Crc.extract(14),
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(Enable_Crc & (Data_Crc.extract(1) ^ Crc.extract(29))) ^ Crc.extract(13),
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(Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28))) ^ Crc.extract(12),
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(Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(11),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(10),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(9),
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(Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract(8),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(7),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(6),
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(Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract(5),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(4),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(3),
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(Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract( 2),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(1),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(0),
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Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30) ^ Crc.extract(31)),
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Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(30)),
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Enable_Crc & (Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29)),
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Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28))
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)
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}
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CrcError := Crc =/= "hc704dd7b".U // CRC not equal to magic number
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}
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class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC {
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val MTxD = RegInit(0.U(4.W)); io.MTxD := MTxD
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val StopExcessiveDeferOccured = RegInit(false.B)
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val StatusLatch = RegInit(false.B)
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val TxUsedData = RegNext(StartData(0) | StartData(1), false.B); io.TxUsedData := TxUsedData
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val TxDone = RegInit(false.B); io.TxDone := TxDone
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val TxAbort = RegInit(false.B); io.TxAbort := TxAbort
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val MTxEn = RegNext(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.MTxEn := MTxEn
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io.MTxErr := false.B
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val WillTransmit = RegNext(StartPreamble | StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.WillTransmit := WillTransmit// WillTransmit
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io.ResetCollision := ~(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS)
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val ExcessiveDeferOccured = io.TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured
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io.StartTxDone := ~io.Collision & (StateFCS & NibCntEq7 | StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & ~io.CrcEn)
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io.LateCollision := StartJam & ~ColWindow
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io.MaxCollisionOccured := StartJam & ColWindow;
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StateSFD := StatePreamble & NibCntEq15;
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io.StartTxAbort := ExcessiveDeferOccured | io.LateCollision | io.MaxCollisionOccured
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when(~io.TxStartFrm){
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StopExcessiveDeferOccured := false.B
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}.elsewhen(ExcessiveDeferOccured){
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StopExcessiveDeferOccured := true.B
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}
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// Collision Window
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when(~io.Collision & ByteCnt(5,0) === io.CollValid & (StateData(1) | StatePAD & NibCnt.extract(0) | StateFCS & NibCnt.extract(0))){
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ColWindow := false.B
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} .elsewhen(StateIdle | StateIPG){
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ColWindow := true.B
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}
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// Start Window
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when(~io.TxStartFrm){
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StatusLatch := false.B
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} .elsewhen(ExcessiveDeferOccured | StateIdle){
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StatusLatch := true.B
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}
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// Transmit packet done
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when(io.TxStartFrm & ~StatusLatch){
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TxDone := false.B
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}.elsewhen(io.StartTxDone){
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TxDone := true.B
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}
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// Transmit packet abort
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when(io.TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured){
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TxAbort := false.B
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} .elsewhen(io.StartTxAbort){
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TxAbort := true.B
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}
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when( true.B ){
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MTxD := // Transmit nibble
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Mux(
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StateData(0), io.TxData(3,0), // Lower nibble
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Mux(StateData(1), io.TxData(7,4), // Higher nibble
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Mux( StateFCS, Cat(~Crc.extract(28), ~Crc.extract(29), ~Crc.extract(30), ~Crc.extract(31)), // Crc
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Mux(StateJam, 9.U, // Jam pattern
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Mux(
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StatePreamble, Mux(NibCntEq15, "hd".U, 5.U),// SFD,Preamble
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0.U
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)
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)
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)
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)
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)
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}
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val PacketFinished_d = io.StartTxDone | io.LateCollision | io.MaxCollisionOccured | ExcessiveDeferOccured;
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val PacketFinished = RegNext(PacketFinished_d, false.B)
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when(true.B){
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PacketFinished_q := PacketFinished
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}
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}
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