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clean up

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RuigeLee
2023-10-25 16:04:53 +08:00
parent 6e25f934b2
commit 1e6f2df9ae
4 changed files with 2 additions and 8 deletions
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src/main/scala/Switch/mac/MacTx.scala
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@@ -21,7 +21,6 @@ class MacTxIO extends Bundle{
val IPGR1 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR1 (from register)
val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register)
val CollValid = Input(UInt(6.W)) // Valid collision window (from register)
val MaxRet = Input(UInt(4.W)) // Maximum retry number (from register)
val ExDfrEn = Input(Bool()) // Excessive defferal enable (from register)
val MTxD = Output(UInt(4.W)) // Transmit nibble (to PHY)