clean up

src/main/scala/Switch/mac/MAC.scala

@@ -496,7 +496,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   rxethmac.io.MAC                 := r_MAC
   rxethmac.io.r_HASH0             := r_HASH0
   rxethmac.io.r_HASH1             := r_HASH1
-  rxethmac.io.PassAll             := true.B
   rxethmac.io.ControlFrmAddressOK := ControlFrmAddressOK
 
   RxData            := rxethmac.io.RxData

src/main/scala/Switch/mac/MacRx.scala

@@ -16,7 +16,6 @@ class MacRxIO extends Bundle{
   val MAC                 = Input(UInt(48.W))     //  Station Address  
   val r_HASH0             = Input(UInt(32.W)) //  lower 4 bytes Hash Table
   val r_HASH1             = Input(UInt(32.W)) //  upper 4 bytes Hash Table
-  val PassAll             = Input(Bool())
   val ControlFrmAddressOK = Input(Bool())
 
   val RxData          = Output(UInt(8.W))
@@ -206,7 +205,7 @@ trait MacRxFAddrCheck { this: MacRxBase =>
   when(ByteCntEq0){
     AddressMiss := false.B
   } .elsewhen(ByteCntEq7 & RxCheckEn){
-    AddressMiss := (~((io.PassAll & io.ControlFrmAddressOK)));    
+    AddressMiss := (~((io.ControlFrmAddressOK)));    
   }
    
   val IntHash = Mux(CrcHash.extract(5), io.r_HASH1, io.r_HASH0)

src/main/scala/Switch/mac/MacTx.scala

@@ -21,7 +21,6 @@ class MacTxIO extends Bundle{
   val IPGR1           = Input(UInt(7.W))         // Non back to back transmit inter packet gap parameter IPGR1 (from register)
   val IPGR2           = Input(UInt(7.W))         // Non back to back transmit inter packet gap parameter IPGR2 (from register)
   val CollValid       = Input(UInt(6.W))         // Valid collision window (from register)
-  val MaxRet          = Input(UInt(4.W))         // Maximum retry number (from register)
   val ExDfrEn         = Input(Bool())         // Excessive defferal enable (from register)
 
   val MTxD               = Output(UInt(4.W))     // Transmit nibble (to PHY)