上传bugfix

2024-07-02 19:27:43 +08:00
parent bcbaa5b39b
commit 17dd970d47
1 changed files with 1 additions and 1 deletions
--- a/src/main/scala/backBoard/SpiSlv.scala
+++ b/src/main/scala/backBoard/SpiSlv.scala
@@ -137,7 +137,7 @@ with BackBoardSpiSlv{


  io.lvdsSlv.upstream_tx_data_in :=
-    Mux(upCnt === 0.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
+    Mux(upCnt === 0.U | upCnt === 1.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)

  val int = RegInit(false.B); interrupt := int
  when( int ){