diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala
index 7a19cb0..467d487 100644
--- a/src/main/scala/backBoard/SpiSlv.scala
+++ b/src/main/scala/backBoard/SpiSlv.scala
@@ -137,7 +137,7 @@ with BackBoardSpiSlv{
 
 
   io.lvdsSlv.upstream_tx_data_in :=
-    Mux(upCnt === 0.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
+    Mux(upCnt === 0.U | upCnt === 1.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
 
   val int = RegInit(false.B); interrupt := int
   when( int ){